M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

drtio/rt_packets: fix

This commit is contained in:
Sebastien Bourdeauducq 2016-10-22 13:03:35 +08:00
parent 449d1c4dc6
commit aa8e211735
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/gateware/drtio/rt_packets.py
View File

@ -509,8 +509,8 @@ class RTPacketMaster(Module):
rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="INPUT"))
self.submodules += rx_fsm
echo_reply_now = Signal()
self.sync.rtio_rx += self.echo_reply_now.eq(echo_reply_now)
echo_received_now = Signal()
self.sync.rtio_rx += self.echo_received_now.eq(echo_received_now)
rx_fsm.act("INPUT",
If(rx_dp.frame_r,
@ -518,7 +518,7 @@ class RTPacketMaster(Module):
If(rx_dp.packet_last,
Case(rx_dp.packet_type, {
rx_plm.types["error"]: NextState("ERROR"),
rx_plm.types["echo_reply"]: echo_reply_now.eq(1),
rx_plm.types["echo_reply"]: echo_received_now.eq(1),
rx_plm.types["fifo_level_reply"]: NextState("FIFO_LEVEL"),
"default": [
error_not.eq(1),