mirror of https://github.com/m-labs/artiq.git
phaser2: wip
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e981b23548
commit
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@ -2,8 +2,9 @@ from migen import *
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from misoc.interconnect.stream import Endpoint
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from misoc.cores.cordic import Cordic
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from .accu import PhasedAccu
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from .tools import eqh
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from .accu import PhasedAccu, Accu
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from .tools import eqh, Delay
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from .spline import Spline
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class DDSFast(Module):
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@ -66,3 +67,288 @@ class DDSFast(Module):
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]
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self.latency += c[0].latency
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self.gain = c[0].gain
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class DDSFast(Module):
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def __init__(self, width, t_width=None,
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a_width=None, p_width=None, f_width=None,
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a_order=4, p_order=1, f_order=2, parallelism=8):
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if t_width is None:
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t_width = width
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if a_width is None:
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a_width = width + (a_order - 1)*t_width
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if p_width is None:
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p_width = width + (p_order - 1)*t_width
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if f_width is None:
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f_width = width + (f_order + 1)*t_width
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a = Spline(order=a_order, width=a_width)
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p = Spline(order=p_order, width=p_width)
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f = Spline(order=f_order, width=f_width)
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self.submodules += a, p, f
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self.a = a.tri(t_width)
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self.f = f.tri(t_width)
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self.p = p.tri(t_width)
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self.i = [self.a, self.f, self.p]
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self.o = [[Signal((width, True)) for i in range(2)]
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for i in range(parallelism)]
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self.parallelism = parallelism
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self.latency = 0 # will be accumulated
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###
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self.latency += p.latency
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q = PhasedAccu(f_width, parallelism)
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self.submodules += q
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self.latency += q.latency
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da = [Signal((width, True)) for i in range(q.latency)]
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self.sync += [
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If(q.i.stb & q.i.ack,
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eqh(da[0], a.o.a0),
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[da[i + 1].eq(da[i]) for i in range(len(da) - 1)],
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),
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If(p.o.stb & p.o.ack,
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q.i.clr.eq(0),
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),
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If(p.i.stb & p.i.ack,
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q.i.clr.eq(self.clr),
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),
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]
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self.comb += [
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a.o.ack.eq(self.ce),
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p.o.ack.eq(self.ce),
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f.o.ack.eq(self.ce),
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q.i.stb.eq(self.ce),
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eqh(q.i.p, p.o.a0),
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q.i.f.eq(f.o.a0),
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q.o.ack.eq(1),
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]
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c = []
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for i in range(parallelism):
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ci = Cordic(width=width, widthz=p_width,
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guard=None, eval_mode="pipelined")
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self.submodules += ci
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c.append(ci)
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qoi = getattr(q.o, "z{}".format(i))
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self.comb += [
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ci.xi.eq(da[-1]),
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ci.yi.eq(0),
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eqh(ci.zi, qoi),
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eqh(self.o[i][0], ci.xo),
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eqh(self.o[i][1], ci.yo),
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]
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self.latency += c[0].latency
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self.gain = c[0].gain
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class DDSSlow(Module):
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def __init__(self, width, t_width, a_width, p_width, f_width,
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a_order=4, p_order=1, f_order=2):
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a = Spline(order=a_order, width=a_width)
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p = Spline(order=p_order, width=p_width)
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f = Spline(order=f_order, width=f_width)
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self.submodules += a, p, f
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self.a = a.tri(t_width)
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self.f = f.tri(t_width)
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self.p = p.tri(t_width)
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self.i = [self.a, self.f, self.p]
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self.i_names = "a f p".split()
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self.o = [Signal((width, True)) for i in range(2)]
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self.ce = Signal()
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self.clr = Signal()
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self.latency = 0 # will be accumulated
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###
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self.latency += p.latency
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q = Accu(f_width)
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self.latency += q.latency
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da = CEInserter()(Delay)(width, q.latency)
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c = Cordic(width=width, widthz=p_width,
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guard=None, eval_mode="pipelined")
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self.latency += c.latency
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self.gain = c.gain
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self.submodules += q, da, c
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self.sync += [
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If(p.o.stb & p.o.ack,
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q.i.clr.eq(0),
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),
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If(p.i.stb & p.i.ack,
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q.i.clr.eq(self.clr),
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),
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]
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self.comb += [
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da.ce.eq(q.i.stb & q.i.ack),
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a.o.ack.eq(self.ce),
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p.o.ack.eq(self.ce),
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f.o.ack.eq(self.ce),
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q.i.stb.eq(self.ce),
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eqh(da.i, a.o.a0),
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eqh(q.i.p, p.o.a0),
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q.i.f.eq(f.o.a0),
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q.o.ack.eq(1),
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c.xi.eq(da.o),
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c.yi.eq(0),
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eqh(c.zi, q.o.z),
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eqh(self.o[0], c.xo),
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eqh(self.o[1], c.yo),
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]
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class DDS(Module):
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def __init__(self, width, t_width=None,
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a_width=None, p_width=None, f_width=None,
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a_order=4, p_order=1, f_order=2, parallelism=8):
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if t_width is None:
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t_width = width
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if a_width is None:
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a_width = width + (a_order - 1)*t_width
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if p_width is None:
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p_width = width + (p_order - 1)*t_width
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if f_width is None:
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f_width = width + (f_order + 1)*t_width
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self.b = [DDSSlow(width, t_width, a_width, p_width, f_width, a_order,
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p_order, f_order) for i in range(2)]
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p = Spline(order=1, width=p_width)
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f = Spline(order=1, width=f_width)
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self.submodules += self.b, p, f
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self.f0 = f.tri(t_width)
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self.p0 = p.tri(t_width)
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self.i = [self.f0, self.p0]
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self.i_names = "f0 p0".split()
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for i, bi in enumerate(self.b):
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self.i += bi.i
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for ii in bi.i_names:
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self.i_names.append("{}{}".format(ii, i + 1))
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for j in "afp":
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setattr(self, "{}{}".format(j, i + 1), getattr(bi, j))
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self.o = [[Signal((width, True)) for i in range(2)]
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for i in range(parallelism)]
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self.ce = Signal()
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self.clr = Signal()
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self.parallelism = parallelism
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self.latency = 0 # will be accumulated
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###
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self.latency += self.b[0].latency # TODO: f0/p0, q.latency delta
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q = PhasedAccu(f_width, parallelism)
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self.submodules += q
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self.sync += [
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If(p.o.stb & p.o.ack,
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q.i.clr.eq(0),
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),
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If(p.i.stb & p.i.ack,
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q.i.clr.eq(self.clr),
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),
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]
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self.comb += [
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[bi.ce.eq(self.ce) for bi in self.b],
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[bi.clr.eq(self.clr) for bi in self.b],
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p.o.ack.eq(self.ce),
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f.o.ack.eq(self.ce),
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q.i.stb.eq(self.ce),
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eqh(q.i.p, p.o.a0),
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eqh(q.i.f, f.o.a0),
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q.o.ack.eq(1),
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]
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x = self.sat_add(bi.o[0] for bi in self.b)
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y = self.sat_add(bi.o[1] for bi in self.b)
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c = []
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for i in range(parallelism):
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ci = Cordic(width=width, widthz=p_width,
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guard=None, eval_mode="pipelined")
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self.submodules += ci
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c.append(ci)
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qoi = getattr(q.o, "z{}".format(i))
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self.comb += [
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ci.xi.eq(x),
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ci.yi.eq(y),
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eqh(ci.zi, qoi),
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eqh(self.o[i][0], ci.xo),
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eqh(self.o[i][1], ci.yo),
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]
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self.latency += c[0].latency
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self.gain = self.b[0].gain * c[0].gain
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class Config(Module):
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def __init__(self):
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self.cfg = Record([("tap", 5), ("clr", 1), ("iq", 2)])
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self.i = Endpoint(self.cfg.layout)
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self.ce = Signal()
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###
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n = Signal(1 << len(self.i.tap))
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tap = Signal.like(self.i.tap)
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clk = Signal()
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clk0 = Signal()
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self.comb += [
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self.i.ack.eq(1),
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clk.eq(Array(n)[tap]),
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]
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self.sync += [
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clk0.eq(clk),
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self.ce.eq(0),
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If(clk0 ^ clk,
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self.ce.eq(1),
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),
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n.eq(n + 1),
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If(self.i.stb,
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n.eq(0),
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self.cfg.eq(self.i.payload),
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),
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]
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class Channel(Module):
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def __init__(self, width=16, t_width=None, u_order=4, **kwargs):
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if t_width is None:
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t_width = width
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du = Spline(width=width + (u_order - 1)*t_width, order=u_order)
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da = DDS(width, t_width, **kwargs)
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cfg = Config()
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self.submodules += du, da, cfg
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self.i = [cfg.i, du.tri(t_width)] + da.i
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self.i_names = "cfg u".split() + da.i_names
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self.q_i = [Signal((width, True)) for i in range(da.parallelism)]
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self.q_o = [ai[1] for ai in da.o]
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self.o = [Signal((width, True)) for i in range(da.parallelism)]
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self.width = width
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self.parallelism = da.parallelism
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self.latency = da.latency + 1
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self.cordic_gain = da.gain
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###
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# delay du to match da
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ddu = Delay((width, True), da.latency - du.latency)
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self.submodules += ddu
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self.comb += [
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ddu.i.eq(du.o.a0[-width:]),
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da.clr.eq(cfg.cfg.clr),
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da.ce.eq(cfg.ce),
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du.o.ack.eq(cfg.ce),
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]
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# wire up outputs and q_{i,o} exchange
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for oi, ai, qi in zip(self.o, da.o, self.q_i):
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self.sync += [
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oi.eq(self.sat_add([
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ddu.o +
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# du.o.a0[-width:],
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Mux(cfg.cfg.iq[0], ai[0], 0),
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Mux(cfg.cfg.iq[1], qi, 0)])),
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]
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def connect_q(self, buddy):
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for i, qi in enumerate(self.q_i):
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self.comb += qi.eq(buddy.q_o[i])
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@ -3,20 +3,21 @@ from collections import namedtuple
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from migen import *
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from artiq.gateware.rtio import rtlink
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from artiq.gateware.dsp.sawg import DDSFast
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from artiq.gateware.dsp.sawg import Channel as _Channel
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_Phy = namedtuple("Phy", "rtlink probes overrides")
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DDSFast_rtio = ClockDomainsRenamer("rio_phy")(DDSFast)
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_ChannelPHY = ClockDomainsRenamer("rio_phy")(_Channel)
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class Channel(DDSFast_rtio):
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class Channel(_ChannelPHY):
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def __init__(self, *args, **kwargs):
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DDSFast_rtio.__init__(self, *args, **kwargs)
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_ChannelPHY.__init__(self, *args, **kwargs)
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self.phys = []
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for i in self.i:
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rl = rtlink.Interface(rtlink.OInterface(len(i.payload)))
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rl = rtlink.Interface(rtlink.OInterface(
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min(32, len(i.payload)))) # TODO: test/expand
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self.comb += [
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i.stb.eq(rl.o.stb),
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rl.o.busy.eq(~i.ack),
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@ -24,4 +25,5 @@ class Channel(DDSFast_rtio):
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]
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# no probes, overrides
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self.phys.append(_Phy(rl, [], []))
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self.phys_names = dict(zip("afp", self.phys))
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self.phys_names = dict(zip("cfg f0 p0 a1 f1 p1 a2 f2 p2".split(),
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self.phys))
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