mirror of https://github.com/m-labs/artiq.git
gateware: reverse SDRAM words in RTIO DMA engine.
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4b14887ddb
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6b63322106
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@ -7,6 +7,10 @@ from misoc.interconnect import stream, wishbone
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from artiq.gateware.rtio import cri
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def _reverse_signal(s):
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return Cat(s[i] for i in reversed(range(len(s))))
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class WishboneReader(Module):
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def __init__(self, bus=None):
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if bus is None:
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@ -35,7 +39,7 @@ class WishboneReader(Module):
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If(self.source.ack, data_reg_loaded.eq(0)),
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If(bus.ack,
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data_reg_loaded.eq(1),
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self.source.data.eq(bus.dat_r),
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self.source.data.eq(_reverse_signal(bus.dat_r)),
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self.source.eop.eq(self.sink.eop)
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)
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]
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@ -23,7 +23,7 @@ def encode_record(channel, timestamp, address, data):
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r += encode_n(channel, 3, 3)
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r += encode_n(timestamp, 8, 8)
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r += encode_n(address, 2, 2)
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r += encode_n(data, 1, 64)
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r += encode_n(data, 4, 64)
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return encode_n(len(r)+1, 1, 1) + r
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@ -33,7 +33,12 @@ def pack(x, size):
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n = 0
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for j, w in enumerate(x[i*size:(i+1)*size]):
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n |= w << j*8
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r.append(n)
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nr = 0
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for i in range(size*8):
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if (n >> i) & 1: nr |= 1 << (size*8 - 1 - i)
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# print("{:064x}".format(n))
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# print("{:064x}".format(nr))
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r.append(nr)
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return r
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@ -48,6 +53,7 @@ class TB(Module):
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def __init__(self, ws):
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sequence = [b for write in test_writes for b in encode_record(*write)]
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sequence.append(0)
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# print(sequence)
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sequence = pack(sequence, ws)
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bus = wishbone.Interface(ws*8)
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