mirror of https://github.com/m-labs/artiq.git
rtio: fix DMA get_csrs
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@ -376,6 +376,6 @@ class DMA(Module):
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)
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def get_csrs(self):
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return ([self.enable, self.busy] +
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return ([self.enable] +
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self.dma.get_csrs() + self.time_offset.get_csrs() +
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self.cri_master.get_csrs())
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