mirror of https://github.com/m-labs/artiq.git
rtio: remove unused clk_freq argument
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parent
5b50f5fe05
commit
fe6a5c42df
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@ -300,8 +300,7 @@ class _KernelCSRs(AutoCSR):
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class RTIO(Module):
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def __init__(self, channels, clk_freq, full_ts_width=63,
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guard_io_cycles=20):
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def __init__(self, channels, full_ts_width=63, guard_io_cycles=20):
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data_width = max(rtlink.get_data_width(c.interface)
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for c in channels)
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address_width = max(rtlink.get_address_width(c.interface)
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@ -58,8 +58,7 @@ class _NIST_QCx(MiniSoC, AMPSoC):
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.pll_sys)
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self.submodules.rtio = rtio.RTIO(rtio_channels,
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clk_freq=125000000)
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self.submodules.rtio = rtio.RTIO(rtio_channels)
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self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
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self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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@ -128,8 +128,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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# RTIO core
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self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
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self.submodules.rtio = rtio.RTIO(rtio_channels,
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clk_freq=125000000)
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self.submodules.rtio = rtio.RTIO(rtio_channels)
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self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
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self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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