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kc705_drtio_master: fix number of fine RTIO timestamp bits

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Sebastien Bourdeauducq 2016-11-28 15:18:54 +08:00
parent 85f2467e2c
commit f4c6d6eb69
1 changed files with 1 additions and 1 deletions
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artiq/gateware/targets/kc705_drtio_master.py
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@ -54,7 +54,7 @@ class Master(MiniSoC, AMPSoC):
phy = ttl_simple.Inout(platform.request(sma))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_core = rtio.Core(rtio_channels, 4)
self.submodules.rtio_core = rtio.Core(rtio_channels, 2)
self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri])
self.submodules.rtio = rtio.KernelInitiator(self.cridec.master)