kc705_drtio_master: add missing rtio_core CSRs

2016-12-09 19:23:36 +08:00 · 2016-12-09 19:23:36 +08:00 · 0a9f69a3ed
parent 4422b6902a
commit 0a9f69a3ed
1 changed files with 1 additions and 0 deletions
--- a/artiq/gateware/targets/kc705_drtio_master.py
+++ b/artiq/gateware/targets/kc705_drtio_master.py
@ -100,6 +100,7 @@ class Master(MiniSoC, AMPSoC):
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))
        self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
+        self.csr_devices.append("rtio_core")

        self.submodules.rtio = rtio.KernelInitiator()
        self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())