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kc705_drtio_master: add missing rtio_core CSRs
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@ -100,6 +100,7 @@ class Master(MiniSoC, AMPSoC):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
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