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drtio: aux controller fixes

This commit is contained in:
Sebastien Bourdeauducq 2016-11-16 19:44:03 +08:00
parent 7fa9a4efc3
commit 140bb0ecee
1 changed files with 10 additions and 4 deletions
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14
artiq/gateware/drtio/aux_controller.py
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@ -111,11 +111,17 @@ class Receiver(Module, AutoCSR):
self.submodules += converter
# when continuously drained, the Converter accepts data continuously
frame_r = Signal()
self.sync.rtio_rx += [
converter.sink.stb.eq(link_layer.rx_aux_stb & link_layer.rx_aux_frame),
converter.sink.data.eq(link_layer.rx_aux_data)
If(link_layer.rx_aux_stb,
frame_r.eq(link_layer.rx_aux_frame),
converter.sink.data.eq(link_layer.rx_aux_data)
)
]
self.comb += [
converter.sink.stb.eq(link_layer.rx_aux_stb & frame_r),
converter.sink.eop.eq(converter.sink.stb & ~link_layer.rx_aux_frame)
]
self.comb += converter.sink.eop.eq(link_layer.rx_aux_stb & ~link_layer.rx_aux_frame)
mem_port = self.mem.get_port(write_capable=True, clock_domain="rtio_rx")
self.specials += mem_port
@ -136,7 +142,7 @@ class Receiver(Module, AutoCSR):
signal_frame = PulseSynchronizer("rtio_rx", "sys")
frame_ack = PulseSynchronizer("sys", "rtio_rx")
signal_error = PulseSynchronizer("rtio_rx", "sys")
self.submodules += signal_frame, signal_error
self.submodules += signal_frame, frame_ack, signal_error
self.sync += [
If(self.aux_rx_present.re, self.aux_rx_present.w.eq(0)),
If(signal_frame.o, self.aux_rx_present.w.eq(1)),