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https://github.com/m-labs/artiq.git
synced 2024-12-25 03:08:27 +08:00
qc2: swap SPI/TTL, all TTL lines are now In+Out compatible
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@ -9,7 +9,7 @@ __all__ = ["fmc_adapter_io"]
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ttl_pins = [
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"LA00_CC_P", "LA02_P", "LA00_CC_N", "LA02_N", "LA01_CC_P", "LA01_CC_N", "LA06_P", "LA06_N",
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"LA05_P", "LA05_N", "LA10_P", "LA09_P", "LA10_N", "LA09_N", "LA13_P", "LA14_P",
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"LA27_P", "LA26_P", "LA27_N", "LA26_N"
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"LA13_N", "LA14_N", "LA17_CC_P", "LA17_CC_N"
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]
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@ -53,19 +53,19 @@ def get_fmc_adapter_io():
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("clkout", next(clkout), FPins("FMC:CLK1_M2C_P"),
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IOStandard("LVTTL")),
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("spi", next(spi),
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Subsignal("clk", FPins("FMC:LA13_N")),
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Subsignal("mosi", FPins("FMC:LA14_N")),
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Subsignal("miso", FPins("FMC:LA17_CC_P")),
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Subsignal("cs_n", FPins("FMC:LA17_CC_N")),
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IOStandard("LVTTL")),
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("spi", next(spi),
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Subsignal("clk", FPins("FMC:LA18_CC_P")),
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Subsignal("mosi", FPins("FMC:LA18_CC_N")),
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Subsignal("miso", FPins("FMC:LA23_P")),
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Subsignal("cs_n", FPins("FMC:LA23_N")),
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IOStandard("LVTTL")),
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("spi", next(spi),
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Subsignal("clk", FPins("FMC:LA27_P")),
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Subsignal("mosi", FPins("FMC:LA26_P")),
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Subsignal("miso", FPins("FMC:LA27_N")),
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Subsignal("cs_n", FPins("FMC:LA26_N")),
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IOStandard("LVTTL")),
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]
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return r
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@ -310,27 +310,22 @@ class NIST_QC2(_NIST_Ions):
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rtio_channels = []
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clock_generators = []
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for backplane_offset in 0, 20:
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# TTL0-15, 20-35 are In+Out capable
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for i in range(16):
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phy = ttl_serdes_7series.Inout_8X(
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platform.request("ttl", backplane_offset+i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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# TTL16-19, 36-39 are output only
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for i in range(16, 20):
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phy = ttl_serdes_7series.Output_8X(
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platform.request("ttl", backplane_offset+i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# All TTL channels are In+Out capable
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for i in range(40):
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phy = ttl_serdes_7series.Inout_8X(
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platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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# CLK0, CLK1 are for the clock generators, on backplane SMP connectors
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for backplane_offset in range(2):
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# CLK0, CLK1 are for clock generators, on backplane SMP connectors
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for i in range(2):
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phy = ttl_simple.ClockGen(
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platform.request("clkout", backplane_offset))
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platform.request("clkout", i))
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self.submodules += phy
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clock_generators.append(rtio.Channel.from_phy(phy))
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# user SMA on KC705 board
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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@ -339,6 +334,7 @@ class NIST_QC2(_NIST_Ions):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# AMS101 DAC on KC705 XADC header - optional
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ams101_dac = self.platform.request("ams101_dac", 0)
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phy = ttl_simple.Output(ams101_dac.ldac)
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self.submodules += phy
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@ -104,9 +104,7 @@ With the QC2 hardware, the TTL lines are mapped as follows:
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+--------------------+-----------------------+--------------+
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| RTIO channel | TTL line | Capability |
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+====================+=======================+==============+
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| 0-15, 20-35 | TTL0-15, TTL20-35 | Input+Output |
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+--------------------+-----------------------+--------------+
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| 16-19, 36-39 | TTL16-19, TTL36-39 | Output |
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| 0-39 | TTL0-39 | Input+Output |
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+--------------------+-----------------------+--------------+
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| 40 | SMA_GPIO_N | Input+Output |
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+--------------------+-----------------------+--------------+
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