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dsp/sat_add: make width mandatory

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This commit is contained in:
Robert Jördens 2017-06-22 17:28:39 +02:00
parent 9b940aa876
commit cd2ac53bc5
2 changed files with 8 additions and 4 deletions
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3
artiq/gateware/dsp/sawg.py
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@ -184,8 +184,10 @@ class Channel(Module, SatAddMixin):
]
self.sync += [
hbf[0].i.eq(self.sat_add((a1.xo[0], a2.xo[0]),
width=len(hbf[0].i),
limits=cfg.limits[1], clipped=cfg.clipped[1])),
hbf[1].i.eq(self.sat_add((a1.yo[0], a2.yo[0]),
width=len(hbf[1].i),
limits=cfg.limits[1], clipped=cfg.clipped[1])),
]
# wire up outputs and q_{i,o} exchange
@ -200,6 +202,7 @@ class Channel(Module, SatAddMixin):
]
self.sync += [
o.eq(self.sat_add((o_offset, o_x, o_y),
width=len(o),
limits=cfg.limits[0], clipped=cfg.clipped[0])),
]

9
artiq/gateware/dsp/tools.py
View File

@ -30,14 +30,15 @@ def eqh(a, b):
class SatAddMixin:
"""Signed saturating addition mixin"""
def sat_add(self, a, *, width=None, limits=None, clipped=None):
def sat_add(self, a, width, limits=None, clipped=None):
a = list(a)
# assert all(value_bits_sign(ai)[1] for ai in a)
if width is None:
width = max(value_bits_sign(ai)[0] for ai in a)
max_width = max(value_bits_sign(ai)[0] for ai in a)
carry = log2_int(len(a), need_pow2=False)
full = Signal((width + carry, True))
full = Signal((max_width + carry, True))
limited = Signal((width, True))
carry = len(full) - width
assert carry >= 0
clip = Signal(2)
sign = Signal()
if clipped is not None: