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drtio: simpler link layer
This commit is contained in:
parent
09363e1da8
commit
bb047aabe9
@ -6,10 +6,9 @@ from artiq.gateware.drtio import link_layer, rt_packets, iot, rt_controller, aux
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class DRTIOSatellite(Module):
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def __init__(self, transceiver, rx_synchronizer, channels, fine_ts_width=3, full_ts_width=63,
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ll_rx_ready_confirm=1000):
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def __init__(self, transceiver, rx_synchronizer, channels, fine_ts_width=3, full_ts_width=63):
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self.submodules.link_layer = link_layer.LinkLayer(
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transceiver.encoder, transceiver.decoders, ll_rx_ready_confirm)
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transceiver.encoder, transceiver.decoders)
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self.comb += [
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transceiver.rx_reset.eq(self.link_layer.rx_reset),
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self.link_layer.rx_ready.eq(transceiver.rx_ready)
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@ -52,9 +51,9 @@ class DRTIOSatellite(Module):
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class DRTIOMaster(Module):
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def __init__(self, transceiver, channel_count=1024, fine_ts_width=3, ll_rx_ready_confirm=1000):
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def __init__(self, transceiver, channel_count=1024, fine_ts_width=3):
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self.submodules.link_layer = link_layer.LinkLayer(
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transceiver.encoder, transceiver.decoders, ll_rx_ready_confirm)
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transceiver.encoder, transceiver.decoders)
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self.comb += [
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transceiver.rx_reset.eq(self.link_layer.rx_reset),
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self.link_layer.rx_ready.eq(transceiver.rx_ready)
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@ -3,43 +3,102 @@ from operator import xor, or_
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.cdc import MultiReg, BusSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.genlib.misc import WaitTimer
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from misoc.interconnect.csr import *
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class Scrambler(Module):
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def __init__(self, n_io, n_state=23, taps=[17, 22]):
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self.i = Signal(n_io)
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self.o = Signal(n_io)
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def __init__(self, n_io1, n_io2, n_state=23, taps=[17, 22]):
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self.i1 = Signal(n_io1)
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self.o1 = Signal(n_io1)
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self.i2 = Signal(n_io2)
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self.o2 = Signal(n_io2)
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self.sel = Signal()
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# # #
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state = Signal(n_state, reset=1)
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curval = [state[i] for i in range(n_state)]
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for i in reversed(range(n_io)):
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flip = reduce(xor, [curval[tap] for tap in taps])
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self.sync += self.o[i].eq(flip ^ self.i[i])
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curval.insert(0, flip)
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curval.pop()
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self.sync += state.eq(Cat(*curval[:n_state]))
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stmts1 = []
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stmts2 = []
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for stmts, si, so in ((stmts1, self.i1, self.o1),
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(stmts2, self.i2, self.o2)):
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curval = [state[i] for i in range(n_state)]
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for i in reversed(range(len(si))):
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out = si[i] ^ reduce(xor, [curval[tap] for tap in taps])
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stmts += [so[i].eq(out)]
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curval.insert(0, out)
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curval.pop()
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stmts += [state.eq(Cat(*curval[:n_state]))]
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self.sync += If(self.sel, stmts2).Else(stmts1)
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class Descrambler(Module):
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def __init__(self, n_io1, n_io2, n_state=23, taps=[17, 22]):
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self.i1 = Signal(n_io1)
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self.o1 = Signal(n_io1)
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self.i2 = Signal(n_io2)
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self.o2 = Signal(n_io2)
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self.sel = Signal()
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# # #
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state = Signal(n_state, reset=1)
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stmts1 = []
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stmts2 = []
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for stmts, si, so in ((stmts1, self.i1, self.o1),
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(stmts2, self.i2, self.o2)):
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curval = [state[i] for i in range(n_state)]
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for i in reversed(range(len(si))):
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flip = reduce(xor, [curval[tap] for tap in taps])
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stmts += [so[i].eq(si[i] ^ flip)]
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curval.insert(0, si[i])
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curval.pop()
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stmts += [state.eq(Cat(*curval[:n_state]))]
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self.sync += If(self.sel, stmts2).Else(stmts1)
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def K(x, y):
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return (y << 5) | x
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aux_coding_comma = [
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K(28, 5),
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K(28, 0),
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K(28, 1),
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K(28, 2),
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K(23, 7),
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K(27, 7),
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K(29, 7),
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K(30, 7),
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]
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aux_coding_nocomma = [
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K(28, 0),
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K(28, 2),
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K(28, 3),
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K(28, 4),
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K(23, 7),
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K(27, 7),
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K(29, 7),
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K(30, 7),
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]
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class LinkLayerTX(Module):
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def __init__(self, encoder):
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nwords = len(encoder.k)
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# nwords must be a power of 2
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assert nwords & (nwords - 1) == 0
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self.link_init = Signal()
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self.signal_rx_ready = Signal()
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self.aux_frame = Signal()
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self.aux_data = Signal(2*nwords)
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self.aux_ack = Signal()
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@ -49,93 +108,64 @@ class LinkLayerTX(Module):
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# # #
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# Idle and auxiliary traffic use special characters excluding K.28.7,
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# K.29.7 and K.30.7 in order to easily separate the link initialization
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# phase (K.28.7 is additionally excluded as we cannot guarantee its
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# non-repetition here).
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# Idle and auxiliary traffic use special characters defined in the
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# aux_coding_* tables.
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# The first (or only) character uses aux_coding_comma which guarantees
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# that commas appear regularly in the absence of traffic.
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# The subsequent characters, if any (depending on the transceiver
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# serialization ratio) use aux_coding_nocomma which does not contain
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# commas. This permits aligning the comma to the first character at
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# the receiver.
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#
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# A set of 8 special characters is chosen using a 3-bit control word.
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# This control word is scrambled to reduce EMI. The control words have
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# the following meanings:
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# 100 idle/auxiliary framing
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# 0AB 2 bits of auxiliary data
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aux_scrambler = ResetInserter()(CEInserter()(Scrambler(3*nwords)))
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self.submodules += aux_scrambler
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#
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# RT traffic uses D characters and is also scrambled. The aux and RT
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# scramblers are multiplicative and share the same state so that idle
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# or aux traffic can synchronize the RT descrambler.
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scrambler = Scrambler(3*nwords, 8*nwords)
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self.submodules += scrambler
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# scrambler input
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aux_data_ctl = []
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for i in range(nwords):
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aux_data_ctl.append(self.aux_data[i*2:i*2+2])
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aux_data_ctl.append(0)
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self.comb += [
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If(self.aux_frame,
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aux_scrambler.i.eq(Cat(*aux_data_ctl))
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scrambler.i1.eq(Cat(*aux_data_ctl))
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).Else(
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aux_scrambler.i.eq(Replicate(0b100, nwords))
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scrambler.i1.eq(Replicate(0b100, nwords))
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),
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aux_scrambler.reset.eq(self.link_init),
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aux_scrambler.ce.eq(~self.rt_frame),
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scrambler.i2.eq(self.rt_data),
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scrambler.sel.eq(self.rt_frame),
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self.aux_ack.eq(~self.rt_frame)
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]
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# compensate for scrambler latency
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rt_frame_r = Signal()
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self.sync += rt_frame_r.eq(self.rt_frame)
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# scrambler output
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for i in range(nwords):
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scrambled_ctl = aux_scrambler.o[i*3:i*3+3]
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scrambled_ctl = scrambler.o1[i*3:i*3+3]
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if i:
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aux_coding = aux_coding_nocomma
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else:
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aux_coding = aux_coding_comma
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self.sync += [
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encoder.k[i].eq(1),
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If(scrambled_ctl == 7,
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encoder.d[i].eq(K(23, 7))
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).Else(
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encoder.d[i].eq(K(28, scrambled_ctl))
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)
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encoder.d[i].eq(Array(aux_coding)[scrambled_ctl])
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]
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# Real-time traffic uses data characters and is framed by the special
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# characters of auxiliary traffic. RT traffic is also scrambled.
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rt_scrambler = ResetInserter()(CEInserter()(Scrambler(8*nwords)))
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self.submodules += rt_scrambler
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self.comb += [
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rt_scrambler.i.eq(self.rt_data),
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rt_scrambler.reset.eq(self.link_init),
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rt_scrambler.ce.eq(self.rt_frame)
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]
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rt_frame_r = Signal()
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self.sync += [
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rt_frame_r.eq(self.rt_frame),
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self.sync += \
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If(rt_frame_r,
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[k.eq(0) for k in encoder.k],
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[d.eq(rt_scrambler.o[i*8:i*8+8]) for i, d in enumerate(encoder.d)]
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[d.eq(scrambler.o2[i*8:i*8+8]) for i, d in enumerate(encoder.d)]
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)
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]
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# During link init, send a series of 1*K.28.7 (comma) + 31*K.29.7/K.30.7
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# The receiving end configures its transceiver to also place the comma
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# on its LSB, achieving fixed (or known) latency and alignment of
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# packet starts.
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# K.29.7 and K.30.7 are chosen to avoid comma alignment issues arising
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# from K.28.7.
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# K.30.7 is sent instead of K.29.7 to signal the alignment of the local
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# receiver, thus the remote can end its link initialization pattern.
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link_init_r = Signal()
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link_init_counter = Signal(max=32//nwords)
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self.sync += [
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link_init_r.eq(self.link_init),
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If(link_init_r,
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link_init_counter.eq(link_init_counter + 1),
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[k.eq(1) for k in encoder.k],
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If(self.signal_rx_ready,
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[d.eq(K(30, 7)) for d in encoder.d[1:]]
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).Else(
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[d.eq(K(29, 7)) for d in encoder.d[1:]]
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),
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If(link_init_counter == 0,
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encoder.d[0].eq(K(28, 7)),
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).Else(
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If(self.signal_rx_ready,
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encoder.d[0].eq(K(30, 7))
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).Else(
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encoder.d[0].eq(K(29, 7))
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)
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)
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).Else(
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link_init_counter.eq(0)
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)
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]
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class LinkLayerRX(Module):
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@ -144,9 +174,6 @@ class LinkLayerRX(Module):
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# nwords must be a power of 2
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assert nwords & (nwords - 1) == 0
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self.link_init = Signal()
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self.remote_rx_ready = Signal()
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self.aux_stb = Signal()
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self.aux_frame = Signal()
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self.aux_data = Signal(2*nwords)
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@ -156,65 +183,46 @@ class LinkLayerRX(Module):
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# # #
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aux_descrambler = ResetInserter()(CEInserter()(Scrambler(3*nwords)))
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rt_descrambler = ResetInserter()(CEInserter()(Scrambler(8*nwords)))
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self.submodules += aux_descrambler, rt_descrambler
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descrambler = Descrambler(3*nwords, 8*nwords)
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self.submodules += descrambler
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# scrambler input
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all_decoded_aux = []
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for i, d in enumerate(decoders):
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decoded_aux = Signal(3)
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all_decoded_aux.append(decoded_aux)
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if i:
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aux_coding = aux_coding_nocomma
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else:
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aux_coding = aux_coding_comma
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cases = {code: decoded_aux.eq(i) for i, code in enumerate(aux_coding)}
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self.comb += Case(d.d, cases).makedefault()
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self.comb += [
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self.aux_frame.eq(~aux_descrambler.o[2]),
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descrambler.i1.eq(Cat(*all_decoded_aux)),
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descrambler.i2.eq(Cat(*[d.d for d in decoders])),
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descrambler.sel.eq(~decoders[0].k)
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]
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# scrambler output
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self.comb += [
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self.aux_frame.eq(~descrambler.o1[2]),
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self.aux_data.eq(
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Cat(*[aux_descrambler.o[3*i:3*i+2] for i in range(nwords)])),
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self.rt_data.eq(rt_descrambler.o),
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]
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aux_stb_d = Signal()
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rt_frame_d = Signal()
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self.sync += [
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self.aux_stb.eq(aux_stb_d),
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self.rt_frame.eq(rt_frame_d)
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]
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link_init_char = Signal()
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self.comb += [
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link_init_char.eq(
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(decoders[0].d == K(28, 7)) |
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(decoders[0].d == K(29, 7)) |
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(decoders[0].d == K(30, 7))),
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If(decoders[0].k,
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If(link_init_char,
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aux_descrambler.reset.eq(1),
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rt_descrambler.reset.eq(1)
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).Else(
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aux_stb_d.eq(1)
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),
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aux_descrambler.ce.eq(1)
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).Else(
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rt_frame_d.eq(1),
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rt_descrambler.ce.eq(1)
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),
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aux_descrambler.i.eq(Cat(*[d.d[5:] for d in decoders])),
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rt_descrambler.i.eq(Cat(*[d.d for d in decoders]))
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Cat(*[descrambler.o1[3*i:3*i+2] for i in range(nwords)])),
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self.rt_data.eq(descrambler.o2)
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]
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self.sync += [
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self.link_init.eq(0),
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If(decoders[0].k,
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If(link_init_char, self.link_init.eq(1)),
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If(decoders[0].d == K(30, 7),
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self.remote_rx_ready.eq(1)
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).Elif(decoders[0].d != K(28, 7),
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self.remote_rx_ready.eq(0)
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),
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If(decoders[1].d == K(30, 7),
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self.remote_rx_ready.eq(1)
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) if len(decoders) > 1 else None
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).Else(
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self.remote_rx_ready.eq(0)
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)
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self.aux_stb.eq(decoders[0].k),
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self.rt_frame.eq(~decoders[0].k)
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]
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class LinkLayer(Module, AutoCSR):
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def __init__(self, encoder, decoders, rx_ready_confirm_cycles):
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self.link_status = CSRStatus(3)
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def __init__(self, encoder, decoders):
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self.link_status = CSRStatus()
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# control signals, in rtio clock domain
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self.reset = Signal()
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@ -242,6 +250,8 @@ class LinkLayer(Module, AutoCSR):
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self.rx_rt_frame = Signal()
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self.rx_rt_data = rx.rt_data
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# # #
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ready_r = Signal()
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ready_rx = Signal()
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self.sync.rtio += ready_r.eq(self.ready)
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@ -251,8 +261,10 @@ class LinkLayer(Module, AutoCSR):
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self.rx_aux_frame.eq(rx.aux_frame & ready_rx),
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self.rx_rt_frame.eq(rx.rt_frame & ready_rx),
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]
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self.specials += MultiReg(ready_r, self.link_status.status)
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# # #
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wait_scrambler = WaitTimer(15)
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self.submodules += wait_scrambler
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fsm = ClockDomainsRenamer("rtio")(
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ResetInserter()(FSM(reset_state="RESET_RX")))
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@ -260,68 +272,17 @@ class LinkLayer(Module, AutoCSR):
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self.comb += fsm.reset.eq(self.reset)
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rx_remote_rx_ready = Signal()
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rx_link_init = Signal()
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rx.remote_rx_ready.attr.add("no_retiming")
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rx.link_init.attr.add("no_retiming")
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self.specials += [
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MultiReg(rx.remote_rx_ready, rx_remote_rx_ready, "rtio"),
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MultiReg(rx.link_init, rx_link_init, "rtio")
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]
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link_status = BusSynchronizer(3, "rtio", "sys")
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self.submodules += link_status
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self.comb += self.link_status.status.eq(link_status.o)
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wait_confirm = ClockDomainsRenamer("rtio")(
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WaitTimer(rx_ready_confirm_cycles))
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self.submodules += wait_confirm
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signal_rx_ready_margin = ClockDomainsRenamer("rtio")(WaitTimer(15))
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self.submodules += signal_rx_ready_margin
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fsm.act("RESET_RX",
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link_status.i.eq(0),
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tx.link_init.eq(1),
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self.rx_reset.eq(1),
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NextState("WAIT_LOCAL_RX_READY")
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NextState("WAIT_RX_READY")
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||||
)
|
||||
fsm.act("WAIT_LOCAL_RX_READY",
|
||||
link_status.i.eq(1),
|
||||
tx.link_init.eq(1),
|
||||
If(self.rx_ready, NextState("CONFIRM_LOCAL_RX_READY"))
|
||||
fsm.act("WAIT_RX_READY",
|
||||
If(self.rx_ready, NextState("WAIT_SCRAMBLER_SYNC"))
|
||||
)
|
||||
fsm.act("CONFIRM_LOCAL_RX_READY",
|
||||
link_status.i.eq(2),
|
||||
tx.link_init.eq(1),
|
||||
wait_confirm.wait.eq(1),
|
||||
If(wait_confirm.done, NextState("WAIT_REMOTE_RX_READY")),
|
||||
If(~rx_link_init, NextState("RESET_RX"))
|
||||
)
|
||||
fsm.act("WAIT_REMOTE_RX_READY",
|
||||
link_status.i.eq(3),
|
||||
tx.link_init.eq(1),
|
||||
tx.signal_rx_ready.eq(1),
|
||||
If(rx_remote_rx_ready, NextState("ENSURE_SIGNAL_RX_READY"))
|
||||
)
|
||||
# If the transceiver transmits one character per RTIO cycle,
|
||||
# we may be unlucky and signal_rx_ready will transmit a comma
|
||||
# on the first cycle instead of a "RX ready" character.
|
||||
# Further, we need to ensure the rx.remote_rx_ready
|
||||
# gets through MultiReg to rx_remote_rx_ready at the receiver.
|
||||
# So transmit the "RX ready" pattern for several cycles.
|
||||
fsm.act("ENSURE_SIGNAL_RX_READY",
|
||||
link_status.i.eq(3),
|
||||
tx.link_init.eq(1),
|
||||
tx.signal_rx_ready.eq(1),
|
||||
signal_rx_ready_margin.wait.eq(1),
|
||||
If(signal_rx_ready_margin.done, NextState("WAIT_REMOTE_LINK_UP"))
|
||||
)
|
||||
fsm.act("WAIT_REMOTE_LINK_UP",
|
||||
link_status.i.eq(4),
|
||||
If(~rx_link_init, NextState("READY"))
|
||||
fsm.act("WAIT_SCRAMBLER_SYNC",
|
||||
wait_scrambler.wait.eq(1),
|
||||
If(wait_scrambler.done, NextState("READY")),
|
||||
)
|
||||
fsm.act("READY",
|
||||
link_status.i.eq(5),
|
||||
If(rx_link_init, NextState("RESET_RX")), # TODO: remove this, link deinit should be detected at upper layer
|
||||
self.ready.eq(1)
|
||||
)
|
||||
|
||||
@ -185,7 +185,7 @@ class GTX_1000BASE_BX10(Module):
|
||||
self.decoders[1].input.eq(rxdata[10:])
|
||||
]
|
||||
|
||||
clock_aligner = BruteforceClockAligner(0b0001111100, self.rtio_clk_freq)
|
||||
clock_aligner = BruteforceClockAligner(0b0101111100, self.rtio_clk_freq)
|
||||
self.submodules += clock_aligner
|
||||
self.comb += [
|
||||
clock_aligner.rxdata.eq(rxdata),
|
||||
|
||||
@ -3,7 +3,7 @@ use sched::{Waiter, Spawner};
|
||||
|
||||
fn drtio_link_is_up() -> bool {
|
||||
unsafe {
|
||||
csr::drtio::link_status_read() == 5
|
||||
csr::drtio::link_status_read() == 1
|
||||
}
|
||||
}
|
||||
|
||||
@ -31,7 +31,10 @@ fn drtio_init_channel(channel: u16) {
|
||||
pub fn link_thread(waiter: Waiter, _spawner: Spawner) {
|
||||
loop {
|
||||
waiter.until(drtio_link_is_up).unwrap();
|
||||
info!("link is up");
|
||||
info!("link RX is up");
|
||||
|
||||
waiter.sleep(300);
|
||||
info!("wait for remote side done");
|
||||
|
||||
drtio_sync_tsc();
|
||||
info!("TSC synced");
|
||||
|
||||
@ -44,13 +44,7 @@ class TestAuxController(unittest.TestCase):
|
||||
dut = TB(4)
|
||||
|
||||
def link_init():
|
||||
yield dut.link_layer.tx.link_init.eq(1)
|
||||
yield
|
||||
yield
|
||||
yield dut.link_layer.tx.link_init.eq(0)
|
||||
while not (yield dut.link_layer.rx.link_init):
|
||||
yield
|
||||
while (yield dut.link_layer.rx.link_init):
|
||||
for i in range(8):
|
||||
yield
|
||||
yield dut.link_layer.ready.eq(1)
|
||||
|
||||
|
||||
@ -41,8 +41,7 @@ class DUT(Module):
|
||||
self.ttl1 = Signal()
|
||||
self.transceivers = DummyTransceiverPair(nwords)
|
||||
|
||||
self.submodules.master = DRTIOMaster(self.transceivers.alice,
|
||||
ll_rx_ready_confirm=15)
|
||||
self.submodules.master = DRTIOMaster(self.transceivers.alice)
|
||||
|
||||
rx_synchronizer = DummyRXSynchronizer()
|
||||
self.submodules.phy0 = ttl_simple.Output(self.ttl0)
|
||||
@ -52,8 +51,7 @@ class DUT(Module):
|
||||
rtio.Channel.from_phy(self.phy1, ofifo_depth=4)
|
||||
]
|
||||
self.submodules.satellite = DRTIOSatellite(
|
||||
self.transceivers.bob, rx_synchronizer, rtio_channels,
|
||||
ll_rx_ready_confirm=15)
|
||||
self.transceivers.bob, rx_synchronizer, rtio_channels)
|
||||
|
||||
|
||||
class TestFullStack(unittest.TestCase):
|
||||
|
||||
@ -22,15 +22,6 @@ def process(seq):
|
||||
return rseq
|
||||
|
||||
|
||||
class TestScrambler(unittest.TestCase):
|
||||
def test_roundtrip(self):
|
||||
seq = list(range(256))*3
|
||||
scrambled_seq = process(seq)
|
||||
descrambled_seq = process(scrambled_seq)
|
||||
self.assertNotEqual(seq, scrambled_seq)
|
||||
self.assertEqual(seq, descrambled_seq)
|
||||
|
||||
|
||||
class Loopback(Module):
|
||||
def __init__(self, nwords):
|
||||
ks = [Signal() for k in range(nwords)]
|
||||
@ -45,12 +36,9 @@ class TestLinkLayer(unittest.TestCase):
|
||||
def test_packets(self):
|
||||
dut = Loopback(4)
|
||||
|
||||
def link_init():
|
||||
yield dut.tx.link_init.eq(1)
|
||||
yield
|
||||
yield
|
||||
yield dut.tx.link_init.eq(0)
|
||||
yield
|
||||
def scrambler_sync():
|
||||
for i in range(8):
|
||||
yield
|
||||
|
||||
rt_packets = [
|
||||
[0x12459970, 0x9938cdef, 0x12340000],
|
||||
@ -59,10 +47,7 @@ class TestLinkLayer(unittest.TestCase):
|
||||
[0x88277475, 0x19883332, 0x19837662, 0x81726668, 0x81876261]
|
||||
]
|
||||
def transmit_rt_packets():
|
||||
while not (yield dut.tx.link_init):
|
||||
yield
|
||||
while (yield dut.tx.link_init):
|
||||
yield
|
||||
yield from scrambler_sync()
|
||||
|
||||
for packet in rt_packets:
|
||||
yield dut.tx.rt_frame.eq(1)
|
||||
@ -78,10 +63,7 @@ class TestLinkLayer(unittest.TestCase):
|
||||
rx_rt_packets = []
|
||||
@passive
|
||||
def receive_rt_packets():
|
||||
while not (yield dut.rx.link_init):
|
||||
yield
|
||||
while (yield dut.rx.link_init):
|
||||
yield
|
||||
yield from scrambler_sync()
|
||||
|
||||
previous_frame = 0
|
||||
while True:
|
||||
@ -100,10 +82,7 @@ class TestLinkLayer(unittest.TestCase):
|
||||
[0xbb, 0xaa, 0xdd, 0xcc, 0x00, 0xff, 0xee]
|
||||
]
|
||||
def transmit_aux_packets():
|
||||
while not (yield dut.tx.link_init):
|
||||
yield
|
||||
while (yield dut.tx.link_init):
|
||||
yield
|
||||
yield from scrambler_sync()
|
||||
|
||||
for packet in aux_packets:
|
||||
yield dut.tx.aux_frame.eq(1)
|
||||
@ -123,10 +102,7 @@ class TestLinkLayer(unittest.TestCase):
|
||||
rx_aux_packets = []
|
||||
@passive
|
||||
def receive_aux_packets():
|
||||
while not (yield dut.rx.link_init):
|
||||
yield
|
||||
while (yield dut.rx.link_init):
|
||||
yield
|
||||
yield from scrambler_sync()
|
||||
|
||||
previous_frame = 0
|
||||
while True:
|
||||
@ -140,8 +116,7 @@ class TestLinkLayer(unittest.TestCase):
|
||||
packet.append((yield dut.rx.aux_data))
|
||||
yield
|
||||
|
||||
run_simulation(dut, [link_init(),
|
||||
transmit_rt_packets(), receive_rt_packets(),
|
||||
run_simulation(dut, [transmit_rt_packets(), receive_rt_packets(),
|
||||
transmit_aux_packets(), receive_aux_packets()])
|
||||
|
||||
# print("RT:")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user