mirror of https://github.com/m-labs/artiq.git
gateware: reset RTIO DMA core when kernel CPU is reset
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parent
200c499114
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28211e0b32
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@ -144,7 +144,8 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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@ -107,7 +107,8 @@ class Master(MiniSoC, AMPSoC):
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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@ -233,7 +233,8 @@ class Phaser(MiniSoC, AMPSoC):
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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# self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
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# self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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# rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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# self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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