mirror of https://github.com/m-labs/artiq.git
Merge branch 'pdq'
* pdq: pdq: documentation pdq2 -> pdq pdq2: use 16 bit data, buffered read_mem() spi: style pdq2: mem_read pdq2: align subsequent writes to end sma_spi: undo cri_con pdq2: memory write, kernel_invariants sma_spi: cri/cd changes sma_spi: LVCMOS25 coredevice.spi: kernel invariants and style sma_spi: free up user_sma pins sma_spi: add demo target with SPI on four SMA pdq2: memory write pdq2: crc/frame register accessors doc: pdq2 spi backend pdq2: config writes
This commit is contained in:
commit
170d2886fd
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@ -0,0 +1,201 @@
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from artiq.language.core import kernel, portable, delay_mu
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from artiq.coredevice import spi
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_PDQ_SPI_CONFIG = (
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0*spi.SPI_OFFLINE | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX
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)
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@portable
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def _PDQ_CMD(board, is_mem, adr, we):
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"""Pack PDQ command fields into command byte.
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:param board: Board address, 0 to 15, with ``15 = 0xf`` denoting broadcast
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to all boards connected.
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:param is_mem: If ``1``, ``adr`` denote the address of the memory to access
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(0 to 2). Otherwise ``adr`` denotes the register to access.
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:param adr: Address of the register or memory to access.
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(``_PDQ_ADR_CONFIG``, ``_PDQ_ADR_FRAME``, ``_PDQ_ADR_CRC``).
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:param we: If ``1`` then write, otherwise read.
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"""
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return (adr << 0) | (is_mem << 2) | (board << 3) | (we << 7)
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_PDQ_ADR_CONFIG = 0
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_PDQ_ADR_CRC = 1
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_PDQ_ADR_FRAME = 2
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class PDQ:
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"""PDQ smart arbitrary waveform generator stack.
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Provides access to a stack of PDQ boards connected via SPI using PDQ
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gateware version 3 or later.
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The SPI bus is wired with ``CS_N`` from the core device connected to
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``F2 IN`` on the master PDQ, ``CLK`` connected to ``F3 IN``, ``MOSI``
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connected to ``F4 IN`` and ``MISO`` (optionally) connected to ``F5 OUT``.
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``F1 TTL Input Trigger`` remains as waveform trigger input.
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Due to hardware constraints, there can only be one board connected to the
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core device's MISO line and therefore there can only be SPI readback
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from one board at any time.
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:param spi_device: Name of the SPI bus this device is on.
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:param chip_select: Value to drive on the chip select lines of the SPI bus
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during transactions.
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"""
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kernel_invariants = {"core", "chip_select", "bus"}
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def __init__(self, dmgr, spi_device, chip_select=1):
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self.core = dmgr.get("core")
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self.bus = dmgr.get(spi_device)
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self.chip_select = chip_select
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@kernel
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def setup_bus(self, write_div=24, read_div=64):
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"""Configure the SPI bus and the SPI transaction parameters
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for this device. This method has to be called before any other method
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if the bus has been used to access a different device in the meantime.
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This method advances the timeline by the duration of two
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RTIO-to-Wishbone bus transactions.
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:param write_div: Write clock divider.
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:param read_div: Read clock divider.
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"""
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# write: 4*8ns >= 20ns = 2*clk (clock de-glitching 50MHz)
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# read: 15*8*ns >= ~100ns = 5*clk (clk de-glitching latency + miso
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# latency)
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self.bus.set_config_mu(_PDQ_SPI_CONFIG, write_div, read_div)
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self.bus.set_xfer(self.chip_select, 16, 0)
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@kernel
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def write_reg(self, adr, data, board):
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"""Set a PDQ register.
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:param adr: Address of the register (``_PDQ_ADR_CONFIG``,
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``_PDQ_ADR_FRAME``, ``_PDQ_ADR_CRC``).
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:param data: Register data (8 bit).
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:param board: Board to access, ``0xf`` to write to all boards.
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"""
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self.bus.write((_PDQ_CMD(board, 0, adr, 1) << 24) | (data << 16))
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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@kernel
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def read_reg(self, adr, board):
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"""Get a PDQ register.
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:param adr: Address of the register (``_PDQ_ADR_CONFIG``,
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``_PDQ_ADR_FRAME``, ``_PDQ_ADR_CRC``).
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:param board: Board to access, ``0xf`` to write to all boards.
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:return: Register data (8 bit).
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"""
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self.bus.set_xfer(self.chip_select, 16, 8)
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self.bus.write(_PDQ_CMD(board, 0, adr, 0) << 24)
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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self.bus.read_async()
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self.bus.set_xfer(self.chip_select, 16, 0)
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return int(self.bus.input_async() & 0xff) # FIXME: m-labs/artiq#713
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@kernel
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def write_config(self, reset=0, clk2x=0, enable=1,
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trigger=0, aux_miso=0, aux_dac=0b111, board=0xf):
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"""Set configuration register.
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:param reset: Reset board (auto-clear).
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:param clk2x: Enable clock double (100 MHz).
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:param enable: Enable the reading and execution of waveform data from
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memory.
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:param trigger: Software trigger, logical OR with ``F1 TTL Input
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Trigger``.
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:param aux_miso: Use ``F5 OUT`` for ``MISO``. If ``0``, use the
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masked logical OR of the DAC channels.
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:param aux_dac: DAC channel mask to for AUX (``F5 OUT``) output.
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:param board: Boards to address, ``0xf`` to write to all boards.
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"""
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config = ((reset << 0) | (clk2x << 1) | (enable << 2) |
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(trigger << 3) | (aux_miso << 4) | (aux_dac << 5))
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self.write_reg(_PDQ_ADR_CONFIG, config, board)
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@kernel
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def read_config(self, board=0xf):
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"""Read configuration register."""
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return self.read_reg(_PDQ_ADR_CONFIG, board)
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@kernel
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def write_crc(self, crc, board=0xf):
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"""Write checksum register."""
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self.write_reg(_PDQ_ADR_CRC, crc, board)
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@kernel
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def read_crc(self, board=0xf):
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"""Read checksum register."""
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return self.read_reg(_PDQ_ADR_CRC, board)
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@kernel
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def write_frame(self, frame, board=0xf):
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"""Write frame selection register."""
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self.write_reg(_PDQ_ADR_FRAME, frame, board)
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@kernel
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def read_frame(self, board=0xf):
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"""Read frame selection register."""
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return self.read_reg(_PDQ_ADR_FRAME, board)
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@kernel
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def write_mem(self, mem, adr, data, board=0xf): # FIXME: m-labs/artiq#714
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"""Write to DAC channel waveform data memory.
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:param mem: DAC channel memory to access (0 to 2).
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:param adr: Start address.
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:param data: Memory data. List of 16 bit integers.
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:param board: Board to access (0-15) with ``0xf = 15`` being broadcast
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to all boards.
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"""
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self.bus.set_xfer(self.chip_select, 24, 0)
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self.bus.write((_PDQ_CMD(board, 1, mem, 1) << 24) |
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((adr & 0x00ff) << 16) | (adr & 0xff00))
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delay_mu(-self.bus.write_period_mu-3*self.bus.ref_period_mu)
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self.bus.set_xfer(self.chip_select, 16, 0)
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for i in data:
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self.bus.write(i << 16)
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delay_mu(-self.bus.write_period_mu)
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delay_mu(self.bus.write_period_mu + self.bus.ref_period_mu)
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# get to 20ns min cs high
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@kernel
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def read_mem(self, mem, adr, data, board=0xf, buffer=8):
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"""Read from DAC channel waveform data memory.
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:param mem: DAC channel memory to access (0 to 2).
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:param adr: Start address.
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:param data: Memory data. List of 16 bit integers.
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:param board: Board to access (0-15) with ``0xf = 15`` being broadcast
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to all boards.
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"""
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n = len(data)
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if not n:
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return
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self.bus.set_xfer(self.chip_select, 24, 8)
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self.bus.write((_PDQ_CMD(board, 1, mem, 0) << 24) |
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((adr & 0x00ff) << 16) | (adr & 0xff00))
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delay_mu(-self.bus.write_period_mu-3*self.bus.ref_period_mu)
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self.bus.set_xfer(self.chip_select, 0, 16)
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for i in range(n):
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self.bus.write(0)
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delay_mu(-self.bus.write_period_mu)
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if i > 0:
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delay_mu(-3*self.bus.ref_period_mu)
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self.bus.read_async()
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if i > buffer:
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data[i - 1 - buffer] = self.bus.input_async() & 0xffff
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delay_mu(self.bus.write_period_mu)
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self.bus.set_xfer(self.chip_select, 16, 0)
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self.bus.read_async()
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for i in range(max(0, n - buffer - 1), n):
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data[i] = self.bus.input_async() & 0xffff
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@ -1,6 +1,6 @@
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import numpy
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from artiq.language.core import (kernel, portable, now_mu, delay_mu)
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from artiq.language.core import kernel, portable, now_mu, delay_mu
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from artiq.language.units import MHz
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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@ -56,9 +56,14 @@ class SPIMaster:
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:param channel: RTIO channel number of the SPI bus to control.
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"""
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kernel_invariants = {"core", "ref_period_mu", "channel"}
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.ref_period_mu = self.core.seconds_to_mu(self.core.coarse_ref_period)
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self.ref_period_mu = self.core.seconds_to_mu(
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self.core.coarse_ref_period)
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assert self.ref_period_mu == self.core.ref_multiplier
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self.channel = channel
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self.write_period_mu = numpy.int64(0)
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self.read_period_mu = numpy.int64(0)
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@ -0,0 +1,157 @@
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#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.build.generic_platform import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from misoc.targets.kc705 import soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.interconnect.csr import *
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from artiq.gateware.amp import build_artiq_soc
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, spi
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from .kc705_dds import _NIST_Ions
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# 10 MHz when using 125MHz input
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self.clock_domains.cd_ext_clkout = ClockDomain(reset_less=True)
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rtio_external_clk = Signal()
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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ext_clkout_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=50, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=ext_clkout_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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Instance("BUFG", i_I=ext_clkout_clk, o_O=self.cd_ext_clkout.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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]
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_sma_spi = [
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("sma_spi", 0,
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Subsignal("clk", Pins("Y23")), # user_sma_gpio_p
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Subsignal("cs_n", Pins("Y24")), # user_sma_gpio_n
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Subsignal("mosi", Pins("L25")), # user_sma_clk_p
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Subsignal("miso", Pins("K25")), # user_sma_clk_n
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IOStandard("LVCMOS25")),
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]
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class SMA_SPI(_NIST_Ions):
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"""
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SPI on 4 SMA for PDQ2 test/demo.
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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platform = self.platform
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self.platform.add_extension(_sma_spi)
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rtio_channels = []
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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ams101_dac = self.platform.request("ams101_dac", 0)
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phy = ttl_simple.Output(ams101_dac.ldac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = spi.SPIMaster(ams101_dac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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phy = spi.SPIMaster(self.platform.request("sma_spi"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=128, ififo_depth=128))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.rtio_crg.cd_rtio.clk.attr.add("keep")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder / "
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"KC705 SMA SPI demo/test for PDQ2")
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builder_args(parser)
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soc_kc705_args(parser)
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args = parser.parse_args()
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soc = SMA_SPI(**soc_kc705_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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if __name__ == "__main__":
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main()
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@ -68,3 +68,9 @@ These drivers are for the core device and the peripherals closely integrated int
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.. automodule:: artiq.coredevice.sawg
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:members:
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:mod:`artiq.coredevice.pdq` module
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-----------------------------------
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.. automodule:: artiq.coredevice.pdq
|
||||
:members:
|
||||
|
|
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