mirror of https://github.com/m-labs/artiq.git
phaser: 10G line rate
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42c6658ffe
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89150c9817
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@ -109,7 +109,7 @@ class DACSetup(EnvExperiment):
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self.ad9154.dac_write(AD9154_SPI_PAGEINDX, 0x3) # A and B dual
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self.ad9154.dac_write(AD9154_INTERP_MODE, 4) # 8x
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self.ad9154.dac_write(AD9154_INTERP_MODE, 3) # 4x
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self.ad9154.dac_write(AD9154_MIX_MODE, 0)
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self.ad9154.dac_write(AD9154_DATA_FORMAT, AD9154_BINARY_FORMAT_SET(0)) # s16
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self.ad9154.dac_write(AD9154_DATAPATH_CTRL,
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@ -198,11 +198,11 @@ class DACSetup(EnvExperiment):
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self.ad9154.dac_write(AD9154_SERDES_SPI_REG, 1)
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self.ad9154.dac_write(AD9154_CDR_OPERATING_MODE_REG_0,
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AD9154_CDR_OVERSAMP_SET(0) | AD9154_CDR_RESERVED_SET(0x2) |
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AD9154_ENHALFRATE_SET(0))
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AD9154_ENHALFRATE_SET(1))
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self.ad9154.dac_write(AD9154_CDR_RESET, 0)
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self.ad9154.dac_write(AD9154_CDR_RESET, 1)
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self.ad9154.dac_write(AD9154_REF_CLK_DIVIDER_LDO,
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AD9154_SPI_CDR_OVERSAMP_SET(0x1) |
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AD9154_SPI_CDR_OVERSAMP_SET(0x0) |
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AD9154_SPI_LDO_BYPASS_FILT_SET(1) |
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AD9154_SPI_LDO_REF_SEL_SET(0))
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self.ad9154.dac_write(AD9154_LDO_FILTER_1, 0x62) # magic
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@ -47,17 +47,17 @@ class StartupKernel(EnvExperiment):
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self.ad9154.clock_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN |
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2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)
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# FPGA deviceclk, dclk/4
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# FPGA deviceclk, dclk/2
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self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)
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self.ad9154.clock_write(AD9516_DIVIDER_4_0,
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(4//2-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
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(4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES)
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(2//2-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
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(2//2-1)*AD9516_DIVIDER_0_LOW_CYCLES)
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self.ad9154.clock_write(AD9516_DIVIDER_4_4, 0*AD9516_DIVIDER_4_DCCOFF)
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self.ad9154.clock_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT |
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2*AD9516_OUT9_LVDS_CMOS_OUTPUT_POLARITY |
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0*AD9516_OUT9_SELECT_LVDS_CMOS)
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# sysref f_data*S/(K*F), dclk/64
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# sysref f_data*S/(K*F), dclk/32
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self.ad9154.clock_write(AD9516_DIVIDER_3_0, (32//2-1)*AD9516_DIVIDER_3_HIGH_CYCLES_1 |
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(32//2-1)*AD9516_DIVIDER_3_LOW_CYCLES_1)
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self.ad9154.clock_write(AD9516_DIVIDER_3_1, 0*AD9516_DIVIDER_3_PHASE_OFFSET_1 |
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@ -398,19 +398,10 @@ class _PhaserCRG(Module, AutoCSR):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.refclk = Signal()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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refclk_pads = platform.request("ad9154_refclk")
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platform.add_period_constraint(refclk_pads.p, 8.)
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self.refclk = Signal()
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self.clock_domains.cd_refclk = ClockDomain()
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self.specials += [
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Instance("IBUFDS_GTE2", i_CEB=0,
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i_I=refclk_pads.p, i_IB=refclk_pads.n, o_O=self.refclk),
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Instance("BUFG", i_I=self.refclk, o_O=self.cd_refclk.clk),
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]
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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@ -419,13 +410,13 @@ class _PhaserCRG(Module, AutoCSR):
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01, p_REF_JITTER2=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=self.cd_refclk.clk,
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p_CLKIN1_PERIOD=4.0, p_CLKIN2_PERIOD=4.0,
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i_CLKIN1=0, i_CLKIN2=self.refclk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=2,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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@ -436,70 +427,95 @@ class _PhaserCRG(Module, AutoCSR):
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),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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MultiReg(pll_locked | ~self._clock_sel.storage,
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self._pll_locked.status)
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]
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class AD9154(Module, AutoCSR):
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def __init__(self, platform, rtio_crg):
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ad9154_spi = platform.request("ad9154_spi")
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self.submodules.spi = spi_csr.SPIMaster(ad9154_spi)
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self.comb += [
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ad9154_spi.en.eq(1),
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platform.request("ad9154_txen", 0).eq(1),
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platform.request("ad9154_txen", 1).eq(1),
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]
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sync_pads = platform.request("ad9154_sync")
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jesd_sync = Signal()
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self.specials += DifferentialInput(
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sync_pads.p, sync_pads.n, jesd_sync)
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self.jesd_sync = jesd_sync
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class AD9154JESD(Module, AutoCSR):
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def __init__(self, platform):
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ps = JESD204BPhysicalSettings(l=4, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
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jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_linerate = 5e9
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jesd_refclk_freq = 125e6
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rtio_freq = 125*1000*1000
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jesd_qpll = GTXQuadPLL(
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rtio_crg.refclk, jesd_refclk_freq, jesd_linerate)
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self.submodules += jesd_qpll
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jesd_phys = []
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settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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linerate = 10e9
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refclk_freq = 250e6
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fabric_freq = 250*1000*1000
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sync_pads = platform.request("ad9154_sync")
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self.jsync = Signal()
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self.refclk = Signal()
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self.specials += DifferentialInput(
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sync_pads.p, sync_pads.n, self.jsync)
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self.clock_domains.cd_jesd = ClockDomain()
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refclk_pads = platform.request("ad9154_refclk")
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platform.add_period_constraint(refclk_pads.p, 1e9/refclk_freq)
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self.specials += [
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Instance("IBUFDS_GTE2", i_CEB=0,
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i_I=refclk_pads.p, i_IB=refclk_pads.n, o_O=self.refclk),
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Instance("BUFR", i_I=self.refclk, o_O=self.cd_jesd.clk),
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AsyncResetSynchronizer(self.cd_jesd, ResetSignal("rio_phy")),
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]
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qpll = GTXQuadPLL(self.refclk, refclk_freq, linerate)
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self.submodules += qpll
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phys = []
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for i in range(4):
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jesd_phy = JESD204BPhyTX(
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jesd_qpll, platform.request("ad9154_jesd", i),
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rtio_freq)
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platform.add_period_constraint(
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jesd_phy.gtx.cd_tx.clk,
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40/jesd_linerate*1e9)
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phy = JESD204BPhyTX(
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qpll, platform.request("ad9154_jesd", i), fabric_freq)
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platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate)
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platform.add_false_path_constraints(
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rtio_crg.cd_rtio.clk,
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jesd_phy.gtx.cd_tx.clk)
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jesd_phys.append(jesd_phy)
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setattr(self.submodules, "jesd_phy"+str(i), jesd_phy)
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self.submodules.jesd_core = JESD204BCoreTX(
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jesd_phys, jesd_settings, converter_data_width=32)
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self.comb += self.jesd_core.start.eq(jesd_sync)
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self.comb += platform.request("user_led", 3).eq(jesd_sync)
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self.submodules.jesd_control = JESD204BCoreTXControl(self.jesd_core)
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self.cd_jesd.clk,
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phy.gtx.cd_tx.clk)
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phys.append(phy)
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to_jesd = ClockDomainsRenamer("jesd")
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self.submodules.core = to_jesd(JESD204BCoreTX(phys, settings,
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converter_data_width=32))
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self.submodules.control = to_jesd(JESD204BCoreTXControl(self.core))
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self.comb += [
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platform.request("ad9154_txen", 0).eq(1),
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platform.request("ad9154_txen", 1).eq(1),
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self.core.start.eq(self.jsync),
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platform.request("user_led", 3).eq(self.jsync),
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]
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# blinking leds for transceiver reset status
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for i in range(4):
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led = platform.request("user_led", 4 + i)
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counter = Signal(32)
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sync = getattr(self.sync, "phy" + str(i))
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counter = Signal(max=fabric_freq//2 + 1)
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sync = getattr(self.sync, "phy{}_tx".format(i))
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sync += \
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If(counter == 0,
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led.eq(~led),
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counter.eq(rtio_freq//2)
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counter.eq(fabric_freq//2)
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).Else(
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counter.eq(counter-1)
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counter.eq(counter - 1)
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)
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class AD9154(Module, AutoCSR):
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def __init__(self, platform):
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ad9154_spi = platform.request("ad9154_spi")
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self.comb += ad9154_spi.en.eq(1)
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self.submodules.spi = spi_csr.SPIMaster(ad9154_spi)
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self.submodules.jesd = AD9154JESD(platform)
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self.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
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self.submodules += self.sawgs
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x = Signal()
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y = Signal()
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self.sync.jesd += x.eq(~x)
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self.sync.rio_phy += y.eq(x)
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for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
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self.comb += conv.eq(Mux(x != y, Cat(ch.o[:2]), Cat(ch.o[2:])))
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class Phaser(_NIST_Ions):
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mem_map = {
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"ad9154": 0x50000000,
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@ -512,7 +528,10 @@ class Phaser(_NIST_Ions):
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platform = self.platform
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platform.add_extension(phaser.fmc_adapter_io)
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sysref_pads = platform.request("ad9154_sysref")
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self.submodules.ad9154 = AD9154(platform)
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self.register_kernel_cpu_csrdevice("ad9154")
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self.config["AD9154_DAC_CS"] = 1 << 0
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self.config["AD9154_CLK_CS"] = 1 << 1
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rtio_channels = []
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@ -525,13 +544,13 @@ class Phaser(_NIST_Ions):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sysref_pads = platform.request("ad9154_sysref")
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phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
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ofifo_depth=2))
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jesd_sync = Signal()
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phy = ttl_simple.Input(jesd_sync)
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phy = ttl_simple.Input(self.ad9154.jesd.jsync)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
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ofifo_depth=2))
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@ -539,29 +558,15 @@ class Phaser(_NIST_Ions):
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
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self.submodules += sawgs
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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for sawg in sawgs
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for sawg in self.ad9154.sawgs
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for phy in sawg.phys)
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels, _PhaserCRG(platform, self.crg.cd_sys.clk))
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to_rtio = ClockDomainsRenamer({"sys": "rtio"})
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self.submodules.ad9154 = to_rtio(AD9154(platform, self.rtio_crg))
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self.register_kernel_cpu_csrdevice("ad9154")
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self.config["AD9154_DAC_CS"] = 1 << 0
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self.config["AD9154_CLK_CS"] = 1 << 1
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for i, ch in enumerate(sawgs):
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conv = getattr(self.ad9154.jesd_core.sink,
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"converter{}".format(i))
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# while at 5 GBps, take every second sample... FIXME
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self.comb += conv.eq(Cat(ch.o[::2]))
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self.comb += jesd_sync.eq(self.ad9154.jesd_sync)
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self.comb += self.rtio_crg.refclk.eq(self.ad9154.jesd.refclk)
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def main():
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