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https://github.com/m-labs/artiq.git
synced 2024-12-28 20:53:35 +08:00
rtio: more DMA fixes, better stopping mechanism
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30bce5ad35
commit
a5834765d0
@ -52,8 +52,6 @@ class DMAReader(Module, AutoCSR):
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# All numbers in bytes
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self.base_address = CSRStorage(aw + data_alignment,
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alignment_bits=data_alignment)
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self.last_address = CSRStorage(aw + data_alignment,
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alignment_bits=data_alignment)
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# # #
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@ -65,18 +63,13 @@ class DMAReader(Module, AutoCSR):
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address.address.eq(self.base_address.storage),
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address.eop.eq(0),
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address.stb.eq(1),
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If(self.base_address.storage == self.last_address.storage,
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address.eop.eq(1)
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)
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),
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If(address.stb & address.ack,
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If(address.eop,
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address.stb.eq(0)
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).Else(
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address.address.eq(address.address + 1),
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If(~enable | (address.address == self.last_address.storage),
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address.eop.eq(1)
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)
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If(~enable, address.eop.eq(1))
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)
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)
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]
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@ -90,12 +83,14 @@ class RawSlicer(Module):
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self.source = Signal(out_size*g)
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self.source_stb = Signal()
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self.source_consume = Signal(max=out_size+1)
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self.flush = Signal()
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self.flush_done = Signal()
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# # #
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# worst-case buffer space required (when loading):
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# <data being shifted out> <new incoming word> <EOP marker>
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buf_size = out_size - 1 + in_size + 1
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# <data being shifted out> <new incoming word>
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buf_size = out_size - 1 + in_size
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buf = Signal(buf_size*g)
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self.comb += self.source.eq(buf[:out_size*8])
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@ -109,9 +104,7 @@ class RawSlicer(Module):
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self.sync += [
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If(load_buf, Case(level,
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# note how the MSBs of the buffer are set to 0
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# (including the EOP marker position)
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{i: buf[i*g:].eq(self.sink.data)
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{i: buf[i*g:(i+in_size)*g].eq(self.sink.data)
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for i in range(out_size)})),
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If(shift_buf, buf.eq(buf >> self.source_consume*g))
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]
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@ -123,12 +116,7 @@ class RawSlicer(Module):
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self.sink.ack.eq(1),
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load_buf.eq(1),
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If(self.sink.stb,
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If(self.sink.eop,
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# insert <granularity> bits of 0 to mark EOP
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next_level.eq(level + in_size + 1)
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).Else(
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next_level.eq(level + in_size)
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)
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next_level.eq(level + in_size)
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),
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If(next_level >= out_size, NextState("OUTPUT"))
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)
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@ -136,10 +124,20 @@ class RawSlicer(Module):
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self.source_stb.eq(1),
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shift_buf.eq(1),
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next_level.eq(level - self.source_consume),
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If(next_level < out_size, NextState("FETCH"))
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If(next_level < out_size, NextState("FETCH")),
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If(self.flush, NextState("FLUSH"))
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)
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fsm.act("FLUSH",
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next_level.eq(0),
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self.sink.ack.eq(1),
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If(self.sink.stb & self.sink.eop,
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self.flush_done.eq(1),
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NextState("FETCH")
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)
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)
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# end marker is a record with length=0
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record_layout = [
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("length", 8), # of whole record (header+data)
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("channel", 24),
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@ -152,34 +150,61 @@ record_layout = [
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class RecordConverter(Module):
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def __init__(self, stream_slicer):
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self.source = stream.Endpoint(record_layout)
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self.end_marker_found = Signal()
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self.flush = Signal()
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hdrlen = layout_len(record_layout) - 512
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record_raw = Record(record_layout)
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self.comb += [
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record_raw.raw_bits().eq(stream_slicer.source),
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self.source.channel.eq(record_raw.channel),
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self.source.timestamp.eq(record_raw.timestamp),
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self.source.address.eq(record_raw.address),
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self.source.data.eq(record_raw.data),
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self.source.stb.eq(stream_slicer.source_stb),
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self.source.eop.eq(record_raw.length == 0),
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If(self.source.ack,
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If(record_raw.length == 0,
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stream_slicer.source_consume.eq(1)
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).Else(
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stream_slicer.source_consume.eq(record_raw.length)
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)
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)
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self.source.data.eq(record_raw.data)
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]
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fsm = FSM(reset_state="FLOWING")
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self.submodules += fsm
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fsm.act("FLOWING",
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If(stream_slicer.source_stb,
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If(record_raw.length == 0,
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NextState("END_MARKER_FOUND")
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).Else(
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self.source.stb.eq(1)
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)
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),
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If(self.source.ack,
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stream_slicer.source_consume.eq(record_raw.length)
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)
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)
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fsm.act("END_MARKER_FOUND",
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self.end_marker_found.eq(1),
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If(self.flush,
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stream_slicer.flush.eq(1),
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NextState("WAIT_FLUSH")
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)
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)
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fsm.act("WAIT_FLUSH",
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If(stream_slicer.flush_done,
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NextState("SEND_EOP")
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)
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)
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fsm.act("SEND_EOP",
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self.source.eop.eq(1),
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self.source.stb.eq(1),
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If(self.source.ack, NextState("FLOWING"))
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)
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class RecordSlicer(Module):
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def __init__(self, in_size):
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self.submodules.raw_slicer = RawSlicer(
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in_size//8, layout_len(record_layout)//8, 8)
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self.submodules.raw_slicer = ResetInserter()(RawSlicer(
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in_size//8, layout_len(record_layout)//8, 8))
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self.submodules.record_converter = RecordConverter(self.raw_slicer)
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self.end_marker_found = self.record_converter.end_marker_found
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self.flush = self.record_converter.flush
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self.sink = self.raw_slicer.sink
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self.source = self.record_converter.source
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@ -199,6 +224,7 @@ class TimeOffset(Module, AutoCSR):
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leave_out={"timestamp"}),
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self.source.payload.timestamp.eq(self.sink.payload.timestamp
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+ self.time_offset.storage),
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self.source.eop.eq(self.sink.eop),
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self.source.stb.eq(self.sink.stb)
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)
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self.comb += [
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@ -260,7 +286,14 @@ class CRIMaster(Module, AutoCSR):
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fsm.act("IDLE",
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If(self.error_status.status == 0,
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If(self.sink.stb, NextState("WRITE"))
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If(self.sink.stb,
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If(self.sink.eop,
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# last packet contains dummy data, discard it
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self.sink.ack.eq(1)
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).Else(
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NextState("WRITE")
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)
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)
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).Else(
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# discard all data until errors are acked
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self.sink.ack.eq(1)
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@ -295,9 +328,7 @@ class CRIMaster(Module, AutoCSR):
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class DMA(Module):
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def __init__(self, membus):
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# shutdown procedure: set enable to 0, wait until busy=0
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self.enable = CSRStorage()
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self.busy = CSRStatus()
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self.enable = CSRStorage(write_from_dev=True)
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self.submodules.dma = DMAReader(membus, self.enable.storage)
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self.submodules.slicer = RecordSlicer(len(membus.dat_w))
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@ -314,17 +345,24 @@ class DMA(Module):
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.comb += self.enable.dat_w.eq(0)
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fsm.act("IDLE",
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If(self.enable.storage, NextState("FLOWING"))
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)
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fsm.act("FLOWING",
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self.busy.status.eq(1),
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If(self.slicer.end_marker_found, self.enable.we.eq(1)),
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If(~self.enable.storage,
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self.slicer.flush.eq(1),
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NextState("WAIT_EOP")
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)
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)
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fsm.act("WAIT_EOP",
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If(self.cri_master.sink.stb & self.cri_master.sink.ack & self.cri_master.sink.eop,
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NextState("WAIT_CRI_MASTER")
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)
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)
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fsm.act("WAIT_CRI_MASTER",
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self.busy.status.eq(1),
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If(~self.cri_master.busy, NextState("IDLE"))
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)
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