mirror of https://github.com/m-labs/artiq.git
pipistrello: use ttl_simple for pmod[4:8]
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@ -180,8 +180,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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pmod = self.platform.request("pmod", 0)
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for i in range(4, 8):
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phy = ttl_serdes_spartan6.Inout_4X(pmod.d[i],
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self.rtio_crg.rtiox4_stb)
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phy = ttl_simple.Inout(pmod.d[i])
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
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ofifo_depth=32))
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