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drtio: fix aux controller clock domain mistakes

This commit is contained in:
Sebastien Bourdeauducq 2016-12-14 10:16:45 +08:00
parent 527757b471
commit e9592105ce
1 changed files with 4 additions and 2 deletions
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6
artiq/gateware/drtio/aux_controller.py
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@ -20,7 +20,8 @@ class Transmitter(Module, AutoCSR):
self.aux_tx = CSR()
self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8))
converter = stream.Converter(mem_dw, ll_dw)
converter = ClockDomainsRenamer("rtio")(
stream.Converter(mem_dw, ll_dw))
self.submodules += converter
# when continuously fed, the Converter outputs data continuously
@ -107,7 +108,8 @@ class Receiver(Module, AutoCSR):
mem_dw = max(min_mem_dw, ll_dw)
self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8))
converter = stream.Converter(ll_dw, mem_dw)
converter = ClockDomainsRenamer("rtio_rx")(
stream.Converter(ll_dw, mem_dw))
self.submodules += converter
# when continuously drained, the Converter accepts data continuously