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drtio: support PHY latency compensation
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parent
497c795d8c
commit
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@ -35,6 +35,13 @@ class IOS(Module):
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fine_ts_width = rtlink.get_fine_ts_width(interface)
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assert fine_ts_width <= max_fine_ts_width
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# latency compensation
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if interface.delay:
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tsc_comp = Signal.like(self.tsc)
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self.sync.rtio += tsc_comp.eq(self.tsc - interface.delay + 1)
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else:
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tsc_comp = self.tsc
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# FIFO
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ev_layout = []
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if data_width:
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@ -69,7 +76,7 @@ class IOS(Module):
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rt_packet.write_underflow.eq(0)),
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If(fifo.we,
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If(~fifo.writable, rt_packet.write_overflow.eq(1)),
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If(rt_packet.write_timestamp[max_fine_ts_width:] < (self.tsc + 4),
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If(rt_packet.write_timestamp[max_fine_ts_width:] < (tsc_comp + 4),
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rt_packet.write_underflow.eq(1)
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)
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)
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@ -86,7 +93,7 @@ class IOS(Module):
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fifo.re.eq(0),
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interface.stb.eq(0),
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If(fifo.readable &
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(fifo_out.timestamp[fine_ts_width:] == self.tsc),
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(fifo_out.timestamp[fine_ts_width:] == tsc_comp),
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fifo.re.eq(1),
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interface.stb.eq(1)
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)
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@ -108,6 +115,13 @@ class IOS(Module):
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selected = Signal()
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self.comb += selected.eq(rt_packet.read_channel == n)
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# latency compensation
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if interface.delay:
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tsc_comp = Signal.like(self.tsc)
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self.sync.rtio += tsc_comp.eq(self.tsc - interface.delay + 1)
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else:
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tsc_comp = self.tsc
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# FIFO
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ev_layout = []
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if data_width:
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@ -130,9 +144,9 @@ class IOS(Module):
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self.comb += fifo_in.data.eq(interface.data)
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if interface.timestamped:
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if fine_ts_width:
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full_ts = Cat(interface.fine_ts, self.tsc)
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full_ts = Cat(interface.fine_ts, tsc_comp)
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else:
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full_ts = self.tsc
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full_ts = tsc_comp
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self.comb += fifo_in.timestamp.eq(full_ts)
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self.comb += fifo.we.eq(interface.stb)
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