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artiq
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pipistrello: add some inputs

old/phaser2
Sebastien Bourdeauducq 2016-11-21 23:43:41 +08:00
parent 6aa5d9f6c6
commit 93c310dfa5
2 changed files with 6 additions and 4 deletions
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6
artiq/gateware/targets/pipistrello.py
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@ -184,9 +184,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
# the last TTL is used for ClockGen
for i in range(15):
if i in (0, 1):
phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
self.rtio_crg.rtiox4_stb)
elif i in (2,): # ttl2 can run on a 8x serdes if xtrig is not used
phy = ttl_serdes_spartan6.Inout_4X(platform.request("ttl", i),
self.rtio_crg.rtiox4_stb)
elif i in (2,):
phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i),
self.rtio_crg.rtiox8_stb)
else:

4
doc/manual/core_device.rst
View File

@ -146,7 +146,9 @@ The TTL lines are mapped to RTIO channels as follows:
+--------------+------------+--------------+
| RTIO channel | TTL line | Capability |
+==============+============+==============+
| 0-14 | B0-14 | Output |
| 0-1 | B0-1 | Input+Output |
+--------------+------------+--------------+
| 2-14 | B2-14 | Output |
+--------------+------------+--------------+
| 15 | USER_LED_1 | Output |
+--------------+------------+--------------+