3d89ba2e11
sayma: remove debug leftover
2018-03-29 10:20:17 +08:00
605292535c
kasli: ignore OSERDESE2->ISERDESE2 timing path on DRTIO targets as well
2018-03-29 10:12:02 +08:00
3a0dfb7fdc
ad53xx: port monitor, moninj dashboard, kc705 target
2018-03-24 16:04:02 +01:00
770b0a7b79
novogorny: conv -> cnv
...
* parity with sampler
* also add novogorny device to opticlock
2018-03-21 18:38:42 +00:00
1afce8c613
kasli: simplify single eem pin formatting
2018-03-21 13:08:42 +01:00
d48b8f3086
kasli: fix sampler sdr/cnv pins
2018-03-21 09:28:00 +00:00
1fb5907362
kasli: add SUServo variant (Sampler-Urukul Servo)
2018-03-21 08:53:26 +00:00
f74d5772f4
sampler: add wide eem definition
2018-03-21 08:53:26 +00:00
32f22f4c9c
sayma: disable SERDES TTL entirely
...
Timing closure becomes very random, even at 4X.
2018-03-21 13:03:48 +08:00
f8c2d54e75
ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma
2018-03-21 13:01:38 +08:00
9c2d343052
sayma: use SERDES RTIO TTL
...
This is not enabled on the standalone design as it breaks timing.
2018-03-21 10:53:52 +08:00
Thomas Harty
37d431039d
Fix typos.
...
Reduce ififo depth to 4 for Zotino.
2018-03-19 09:42:18 +00:00
Thomas Harty
c4fa44bc62
Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 on OptiClock.
2018-03-18 00:25:43 +00:00
Florent Kermarrec
eb6e59b44c
sayma_rtm: fix serwb timing constraints (was causing the gated clock warning)
2018-03-12 11:25:29 +01:00
fc3d97f1f7
drtio: remove spurious multichannel transceiver clock constraints
...
They used to cause (otherwise harmless) Vivado critical warnings.
2018-03-09 22:46:27 +08:00
caf7b14b55
kasli: generate fine RTIO clock in DRTIO targets, separate RTIO channel code
2018-03-09 22:36:16 +08:00
82831a85b6
kasli/opticlock: add eem6 phys
2018-03-07 21:32:59 +01:00
916197c4d7
siphaser: cleanup
2018-03-07 11:15:44 +08:00
7d98864b31
sayma: enable siphaser
2018-03-07 10:57:30 +08:00
a6e29462a8
sayma: enable multilink DRTIO
2018-03-07 10:57:30 +08:00
c34d00cbc9
drtio: implement Si5324 phaser gateware and partial firmware support
2018-03-07 10:57:30 +08:00
994ceca9ff
sayma_amc: disable slave fpga gateware loading
2018-03-06 17:27:43 +01:00
62af7fe2ac
Revert "kasli/opticlock: use plain ttls for channels 8-23"
...
This reverts commit bd5c222569eb68d624a5ac1e9f2542f6ee553f83.
No decrease in power consumption or improvement in timing.
2018-03-06 14:27:19 +01:00
fd3cdce59a
kasli/opticlock: use plain ttls for channels 8-23
2018-03-06 14:27:19 +01:00
956098c213
kasli: add second urukul, make clk_sel drive optional
2018-03-06 14:26:27 +01:00
07de7af86a
kasli: make second eem optional in urukul
2018-03-06 14:26:26 +01:00
ddcc68cff9
sayma_amc: move bitstream options to migen
...
close #930
2018-03-02 18:13:03 +08:00
a9daaad77b
kasli: add SYSU variant and device_db
2018-03-02 14:44:31 +08:00
ec5b81da55
kc705: switch backplane spi to spi2
2018-03-01 11:19:18 +01:00
a7720d05cd
firmware, sayma: port converter_spi to spi2
...
* ksupport/nrt_bus
* port ad9154, hmc830, hmc7043
* port local_spi and drtio_spi
* port kernel_proto libdrtioaux, satman
* change sayma_rtm gateware over
* add spi2 NRTSPIMaster
* remove spi NRTSPIMaster
* change sayma device_db
* change HMC830 to open mode and explicitly sequence open mode
2018-03-01 11:19:18 +01:00
54984f080b
artiq_flash: flash RTM firmware
...
based on whitequark's work in f95fb27m-labs/artiq#813
2018-02-28 19:29:01 +01:00
1f999c7f5f
sayma_amc: expose RTM fpga load pins as GPIOs
2018-02-28 18:44:36 +01:00
386aa75aaa
kasli: control SFP1 and SFP2 LEDs in DRTIO satellite to match master
2018-02-27 23:18:18 +08:00
5d81877b34
kasli: implement multi-link DRTIO on SFP1 and SFP2 of master
2018-02-27 23:15:20 +08:00
e565d3fa59
kasli: add analyzer and RTIO log to DRTIO master target
2018-02-27 18:09:07 +08:00
1452cd7447
novogorny: add coredevice driver and test with Kasli
...
m-labs/artiq#687
2018-02-22 17:19:51 +01:00
3b7971d15d
kasli: spelling
2018-02-22 17:19:51 +01:00
771bf87b56
kc705: port amc101_dac/spi0 and sma_spi to spi2
2018-02-22 17:19:51 +01:00
f8e6b4f4e3
ad5360: port to spi2
...
* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db
This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1
m-labs/artiq#926
2018-02-22 10:25:46 +01:00
fa0d929b4d
drtio: reorganize RX synchronizers
2018-02-22 15:21:23 +08:00
e5de5ef473
kasli: use deterministic RX synchronizer
...
Could not reproduce the "fully broken bitstream" bug.
2018-02-22 15:18:09 +08:00
a5ad1dc266
kc705: fix sdcard miso pullup
2018-02-21 19:41:05 +01:00
0d8145084d
test_spi: move to new spi2 core
2018-02-21 19:41:05 +01:00
a63fd306af
urukul: use spi2
...
* switch kc705 and kasli targets to spi2 gateware on urukul
* rewrite urukul, ad9912, ad9910
* update example experiments, device_dbs
2018-02-21 15:00:28 +00:00
91a4a7b0ee
kasli: free run si5324 on opticlock for now
2018-02-21 13:37:29 +00:00
7e02d8245c
kasli: false paths
...
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
2018-02-19 13:05:11 +00:00
0f4549655b
sayma: use Xilinx RX synchronizer
...
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
2018-02-19 17:49:53 +08:00
3bc575bee7
drtio: add missing define for Sayma master
2018-02-19 17:11:21 +08:00
7376ab0ff8
drtio: fix Sayma after 83abdd28
2018-02-19 17:10:55 +08:00
c329c83676
kasli: fix disable_si5324_ibuf no_retiming
2018-02-19 12:19:05 +08:00
a93decdef2
kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
2018-02-19 00:48:37 +08:00
83abdd283a
drtio: signal stable clock input to transceiver
2018-02-18 22:29:30 +08:00
287d533437
Revert "sayma_amc: remove RTM bitstream upload core. Closes #908 "
...
This reverts commit 2d4a1340ea
2018-02-17 17:38:48 +08:00
73985a9215
sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)
2018-02-17 17:38:17 +08:00
039dee4c8e
si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER
...
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
2018-02-17 13:54:50 +08:00
cfb21ca126
si5324: fix usage of external CLKIN2 reference
2018-02-17 13:52:01 +08:00
e41f49cc75
kasli: opticlock 125 MHz, mark external reference case broken
2018-02-16 17:23:15 +00:00
4d42df2a7c
kasli: set up Si5324 in standalone operation
2018-02-15 20:32:58 +08:00
d7387611c0
sayma: print RTM gateware version
2018-02-15 19:31:58 +08:00
be693bc8a9
opticlock: examples
2018-02-13 22:13:40 +01:00
a3d136d30d
opticlock: wire urukul and novogorny
2018-02-13 22:13:40 +01:00
00f42f912b
rename 'RTM identifier' to 'RTM magic number'
...
Avoids confusion with the MiSoC identifier (containing the ARTIQ version).
2018-02-13 20:02:51 +08:00
2d4a1340ea
sayma_amc: remove RTM bitstream upload core. Closes #908
2018-02-07 12:27:35 +08:00
whitequark
61c64a76be
gateware: use a per-variant subfolder in --output-dir. ( fixes #912 )
...
This commit also adds support for --variant and --args
to artiq-devtool.
2018-02-06 08:19:01 +00:00
whitequark
885ab40946
conda: split RTM and AMC packages back.
...
This avoids multiplying the RTM compilation time by the number
of AMC packages.
2018-01-28 14:27:55 +00:00
whitequark
11a8b84355
Merge the build trees of sayma_amc and sayma_rtm targets.
...
This also makes them a single artiq_flash target, and a single
conda package.
2018-01-27 19:54:31 +00:00
440e19b8f9
kasli: use SFP2 for DRTIO mastering
...
SFP1 PCB routing has some issues.
Also use SFP1 LED for DRTIO in both master and satellite.
2018-01-26 19:02:54 +08:00
e0e795f11c
sayma_amc: constrain pin, remove keep
2018-01-23 15:42:47 +00:00
b5c035bb52
sayma_rtm: constrain serwb clock input
2018-01-23 13:54:53 +00:00
aada38f508
kasli, kc705: remove vivado "keep", cleanup a constraint
2018-01-23 13:15:26 +00:00
85102e191e
sayma_rtm: derive clocks automatically
...
* also don't add false paths unless necessary
2018-01-23 11:00:55 +00:00
7d1b3f37c9
sayma_rtm: set CFGBVS/CONFIG_VOLTAGE, compress
2018-01-23 10:56:42 +00:00
649deccd9b
kasli: fix DRTIO satellite QPLL refclksel
2018-01-23 12:27:19 +08:00
4b4374f76a
sayma: register_jref for JESD204. Closes #904
2018-01-23 12:19:15 +08:00
763aefacff
kasli: fix typo
2018-01-23 12:10:54 +08:00
c7b148a704
kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1
2018-01-23 12:08:10 +08:00
9f87c34a94
kasli: fix QPLL instantiation
2018-01-23 10:39:31 +08:00
031d7ff020
kasli: keep using second QPLL channel for DRTIO satellite
2018-01-23 10:13:10 +08:00
aa62e91487
kasli: add DRTIO targets (no firmware)
2018-01-23 01:27:40 +08:00
296ac35f5d
sayma_amc: SFP TX disable is active-high
2018-01-23 00:32:09 +08:00
77192256ea
kc705: style
2018-01-23 00:02:35 +08:00
ab7c49d6d0
sayma_amc: raise error on invalid variant
2018-01-23 00:02:16 +08:00
c1ac3b66b1
sayma_rtm: fix 8fe463d4a
2018-01-23 00:01:45 +08:00
53facfef13
sayma: build fixes
2018-01-22 18:33:22 +08:00
25f3feeda8
refactor targets
2018-01-22 18:25:10 +08:00
5198c224a2
sayma,kasli: use new pin names
2018-01-22 11:51:07 +08:00
Florent Kermarrec
8fe463d4a0
sayma_rtm: add UART loopback to easily know if rtm fpga is alive
2018-01-20 06:04:34 +01:00
Florent Kermarrec
74ce7319d3
sayma: reduce serwb linerate to 625Mbps (make it work on saymas with 1.8v issue, related?)
2018-01-20 06:04:18 +01:00
cdbf95d46a
kasli: fix permissions
2018-01-19 18:31:20 +08:00
8ec33ae7bd
kasli: feed EEM clock fan-out from SI5324
2018-01-17 17:27:59 +01:00
ed3e3b2791
sayma_amc: clarify --with-sawg help
2018-01-17 12:10:30 +01:00
Florent Kermarrec
f54b27b79c
sayma_amc: prepare for jesd subclass 1
2018-01-17 11:49:36 +01:00
7405006668
sayma: rtio clock is jesd fabric clock
2018-01-16 18:19:04 +01:00
whitequark
444b901dbe
sayma: add RTM configuration port.
2018-01-16 07:28:00 +00:00
whitequark
6891141fa6
artiq_flash: add sayma support.
2018-01-15 11:43:29 +00:00
ac3c3871d0
kasli: s/extensions/variant/g
2018-01-12 12:29:42 +01:00
7c82fcf41a
targets: avoid passing cpu_type around unnecessarily
2018-01-11 11:21:55 +08:00
6d58c4390b
Merge branch 'sed-merge'
2018-01-10 13:14:39 +08:00
04b2fd3e13
sayma: fix AD9154NoSAWG ramp clock domain
2018-01-10 12:11:33 +08:00
dc593ec0f0
Merge branch 'rtio-sed' into sed-merge
2018-01-10 12:04:54 +08:00
8813aee6b1
targets: add kasli [wip, untested]
2018-01-04 16:12:12 +01:00
Florent Kermarrec
1e972034e8
gateware/targets: enable serwb scrambling on sayma amc & rtm
2018-01-03 17:34:46 +01:00
c2be820e9a
kc705_dds: make ext_clkout 100 MHz
2018-01-02 19:58:47 +01:00
43686f324b
kc705_dds: fix HPC voltages
...
* VADJ is 3.3 V due to the DDS card on LPC
* the LVDS standards need to be 2.5 V
* the direction control register on HPC (FMC-DIO to VHDCI)
was LVCMOS33 but while all the LVDS pairs are at VCCIO=VADJ=3.3 V
they were instantiated as LVDS_25 (ignoring the wrongly powered bank)
* we now use 2.5 V standards on HPC consistently despite VADJ=3.3 V
and hope for the best.
2018-01-02 13:41:07 +01:00
94b84ebe7c
kc705_dds: add urukul spi/ttl channels
2018-01-02 13:20:48 +01:00
53969d3686
kc705_dds: add urukul on vhdci extension definition
2018-01-02 13:20:47 +01:00
745e695b09
sayma: output a ramp in the absence of SAWG channels
2017-12-31 12:18:53 +01:00
whitequark
a371b25525
bootloader: allow using without Ethernet.
2017-12-31 09:21:28 +00:00
379d29561b
sayma: plausibility assertion on sawg data stream
2017-12-29 19:15:40 +01:00
6801921fc0
drtio: instrument GTH transceiver
2017-12-28 15:03:14 +08:00
70b7f28ad3
drtio: drive SFP TX disable pins
2017-12-23 22:58:51 +08:00
1af21c0b29
drtio: integrate GTH transceiver for Sayma
2017-12-23 01:19:59 +08:00
ebdbaaad32
drtio: remove KC705/GTX support
2017-12-22 17:51:42 +08:00
0681d472c7
conda: fix sayma_rtm_csr.csv location for Sayma AMC
2017-12-22 17:14:10 +08:00
44959144d8
conda: add Sayma AMC standalone board package
2017-12-22 16:44:04 +08:00
Florent Kermarrec
86825a852c
gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200
2017-12-21 23:52:44 +01:00
a6ffe9f38d
drtio: add Sayma top-level designs
2017-12-21 23:08:56 +08:00
4fbc8772a5
sayma: allocate all user LEDs to RTIO, make one TTL SMA input
2017-12-21 19:27:38 +08:00
a23251276d
Revert "sayma: set up Si5324 for RGMII clock rerouting"
...
This reverts commit 2b01aa22b6
2017-12-21 14:42:15 +08:00
2b01aa22b6
sayma: set up Si5324 for RGMII clock rerouting
2017-12-17 00:25:33 +08:00
b6199bb35b
sayma: style
2017-12-15 19:45:51 +08:00
649b60ea29
targets/kc705_drtio: remove DAC FMC card support
2017-12-15 17:32:25 +08:00
341e809859
targets/sayma_rtm: enable Allaki RF switches, GPIO access to attenuator
2017-12-15 13:08:35 +08:00
569484f888
remove phaser, adapt SAWG example to Sayma
2017-12-14 18:49:27 +08:00
5e251cd85c
sayma_amc: remove redundant bitstream options
...
* CONFIGRATE default is sufficient
* SPI width can be auto and QSPI works
2017-12-13 14:39:32 +01:00
a9d0f253a5
sayma_amc: set bitstream and config parameters
...
* slow down CCLK rate as there is additional loading
on the signals
* single bit SPI for now until we know that quad SPI
works
* set up
https://github.com/m-labs/artiq/issues/847
2017-12-13 21:21:52 +08:00
bb3d6ef84a
sayma: remove ad9154 from mem_map
...
Address is autogenerated by CSR system.
2017-11-29 18:17:25 +08:00
ecfe2e40ee
sayma_amc_standalone: rtio channels for both sawg groups
2017-11-19 18:32:42 +01:00
d1a7c1c3a1
sayma_amc_standalone: connect sawg to jesd again
2017-11-19 14:36:20 +01:00
Florent Kermarrec
dfdd2dd9e6
gateware/targets/sayma_amc_standalone: revert self.add_wb_slave on serwb
2017-11-19 09:01:20 +01:00
Florent Kermarrec
cd83b71d92
gateware/targets/sayma_amc_standalone: serwb working, need fixing on AD9154 data mapping
2017-11-18 18:10:28 +01:00
Florent Kermarrec
464b24a608
gateware/targets/sayma_amc: integrate ad9154 correctly (add crg, use cpll instead of qpll, use correct clocking) and cleanup serwb constraints.
2017-11-10 10:48:32 +01:00
Florent Kermarrec
278c739d30
gateware/targets/sayma_rtm: add dynamic clock mux, cleanup serwb clock constraints
2017-11-10 10:39:47 +01:00
Florent Kermarrec
76ddb063cf
gateware/targets/sayma: get hmc830/7043 spi working (still need to test clock generation)
2017-11-06 12:08:28 +01:00
d80cf8d59d
kc705: add TTLs and shift register driver for FMC DIO
2017-10-31 23:14:39 +08:00
412548a86c
gateware: add AD5360 monitor (untested)
2017-10-23 20:09:28 +08:00
5803ac9998
gateware: add Zotino SPI to NIST CLOCK target
2017-10-23 15:04:30 +08:00
c7de233208
Merge Sayma SAWG changes (untested)
...
See #798
* sinara:
conda: bump migen
sayma_amc: SAWG (untested)
sayma_rtm: make build dir
conda: jesd204b 0.4
2017-09-29 21:01:02 +02:00
b4c52c34f7
Merge branch 'sinara'
2017-09-30 01:11:16 +08:00
5e3cc83842
sayma_amc: SAWG (untested)
2017-09-27 18:44:35 +02:00
2604806512
sayma_rtm: make build dir
2017-09-27 18:35:46 +02:00
aa8fc81a87
rtio: allow specifying glbl_fine_ts_width externally
2017-09-23 22:34:55 +08:00
7249f151a5
targets/kc705_drtio_satellite: add missing shebang line
2017-09-19 20:48:12 +08:00
1ff10785dc
targets/kc705_drtio_satellite: add missing shebang line
2017-09-19 20:46:16 +08:00
0824e0aeae
gateware/targets: remove deprecated ofifo_depth parameter
2017-09-16 17:04:11 +08:00
Florent Kermarrec
2091c7696a
artiq/gateware/targets/sayma_amc_standalone: fix serwb_pll vco_div and serwb_phy mode
2017-09-06 09:18:12 +02:00
0a5904bbaa
firmware: support for multiple JESD DACs
2017-08-31 13:05:48 +08:00
a4144a07c4
sayma_amc: add converter SPI config defines
2017-08-31 13:04:38 +08:00
bacf8a1614
style
2017-08-31 12:52:09 +08:00
ad0a940e2d
sayma_rtm: hook up DAC SPI
2017-08-31 11:48:54 +08:00
f765dc50de
sayma_rtm: do not keep DACs in reset
2017-08-31 11:44:33 +08:00
a67659338d
sayma: clean up serwb comments
2017-08-31 11:42:01 +08:00
Florent Kermarrec
9650233007
gateware/serwb: change serdes clock domain to serwb_serdes
2017-08-30 15:44:44 +02:00
Florent Kermarrec
32ca51faee
gateware/targets/sayma_amc_standalone/rtm: use new serwb modules
2017-08-30 15:25:20 +02:00
Florent Kermarrec
60ad36e7d6
gateware/serwb: generate wishbone error on wishbone slave when access while link is not ready
2017-08-29 13:43:26 +02:00
26a11a296c
sayma_rtm: drive DAC control signals
2017-08-26 16:57:02 -07:00
d609c67cbd
sayma_rtm: set clock mux pins
2017-08-26 16:48:10 -07:00
9194402ea5
sayma_rtm: expose HMC SPI bus
2017-08-26 16:31:31 -07:00
dbc12540da
sayma_amc: register RTM CSR regions from CSV
2017-08-26 14:48:11 -07:00
54c75d3274
sayma_rtm: use CSR infrastructure, generate CSR CSV
2017-08-23 17:19:53 -04:00
668450db26
sayma_amc: add serwb
2017-08-21 18:11:29 -04:00
0459a70cf6
sayma_amc: cleanup, fix RTM UART forwarding
2017-08-21 16:49:42 -04:00
1f2b373d09
sayma_rtm: remove unnecessary serwb_control
2017-08-21 16:37:13 -04:00
bfea297279
targets: add Sayma RTM
2017-08-21 15:58:01 -04:00
d6b624dfbe
sayma_amc: connect RTM serial and second serial
2017-08-20 19:01:55 -04:00
bee4902323
add Sayma AMC standalone target
2017-08-20 11:47:45 -04:00
1dab7df846
kc705_sma_spi: fix permissions
2017-08-20 10:54:24 -04:00
df4f38a1e4
kc705: add pullup on SD card MISO
2017-07-24 22:26:16 +08:00
a201a9abd9
drtio: multilink transceiver interface
2017-07-18 13:27:33 +08:00
9045b4cc19
drtio: initial firmware support for multi-link
2017-07-18 00:40:21 +08:00
4deb5f6a45
gateware: use new MiSoC Wishbone address system
2017-07-13 19:16:49 +08:00
mntng
40ca951750
kc705: add SPI bus for memory card
...
This will be useful for SPI unit tests using a SD card as victim.
2017-07-12 00:27:44 +08:00
ff0da2c9fc
sawg: stage code for y-data exchange on channels
2017-06-22 10:26:29 +02:00
74cf074538
drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times
2017-06-21 17:01:52 +08:00
bfc224d4ba
phaser: adjust to new jesd
2017-05-22 19:59:53 +02:00
679060af1d
phaser: enable dma
2017-05-22 19:32:34 +02:00
9ab63920e0
Remove Pipistrello support
...
Closes #658
Closes #381
2017-05-15 17:17:44 +08:00
170d2886fd
Merge branch 'pdq'
...
* pdq:
pdq: documentation
pdq2 -> pdq
pdq2: use 16 bit data, buffered read_mem()
spi: style
pdq2: mem_read
pdq2: align subsequent writes to end
sma_spi: undo cri_con
pdq2: memory write, kernel_invariants
sma_spi: cri/cd changes
sma_spi: LVCMOS25
coredevice.spi: kernel invariants and style
sma_spi: free up user_sma pins
sma_spi: add demo target with SPI on four SMA
pdq2: memory write
pdq2: crc/frame register accessors
doc: pdq2 spi backend
pdq2: config writes
2017-05-12 11:46:45 +02:00
Florent Kermarrec
79c339d4ac
gateware/targets/phaser: jesd core now handles jsync completely
2017-04-26 22:25:08 +02:00
Florent Kermarrec
0546affd4c
gateware/target/phaser: jesd start signal renamed to jsync
2017-04-26 12:27:40 +02:00
ed8edf318d
sma_spi: undo cri_con
2017-04-08 17:19:35 +02:00
16b7f8f50c
sma_spi: cri/cd changes
2017-04-08 17:16:19 +02:00
1e6e81a19e
sma_spi: LVCMOS25
2017-04-08 17:16:19 +02:00
555b3c38c1
sma_spi: free up user_sma pins
2017-04-08 17:16:19 +02:00
2c7c6143ab
sma_spi: add demo target with SPI on four SMA
2017-04-08 17:16:19 +02:00
674bf82f3a
gateware: add cri_con CSRs to all DMA-capable targets
2017-04-06 01:14:09 +08:00
whitequark
464202d0aa
gateware: connect CRI switch to kernel CPU.
2017-04-05 16:10:53 +00:00
whitequark
391660e545
gateware: simplify the CRI arbiter to use a plain mux.
2017-04-05 15:09:19 +00:00
28211e0b32
gateware: reset RTIO DMA core when kernel CPU is reset
2017-03-31 15:35:28 +08:00
a7de58b604
rtio: Inout → InOut
2017-03-14 14:18:55 +08:00
d2f2415b50
analyzer: use CRI and connect at RTIO core
...
This causes DMA events to be included in analyzer traces.
2017-03-02 18:47:56 +08:00
f017d1771f
gateware: remove unused configs in targets (not needed with new moninj)
2017-02-25 12:14:56 +08:00
360be0098f
drtio: map local RTIO core on lower channels
2017-02-24 18:15:27 +08:00
b455ea447d
gateware: add moninj to drtio targets
2017-02-21 21:54:47 +08:00
935799dfb7
drtio: fix satellite transceiver clocking
2017-02-04 19:18:35 +08:00
a8ecbd6041
firmware: do not attempt to build Si5324 code when gateware does not support it
2017-02-03 12:27:13 +08:00
d181989de9
drtio: reset Si5324 at each boot
2017-02-03 12:00:58 +08:00
b3697f951a
drtio: forward clocks to SMA connectors for debugging
2017-02-03 12:00:36 +08:00
aafefee7f5
targets: make number of ethmac slots consistent
2017-02-02 23:02:51 +08:00
whitequark
44a9a79f96
firmware: port allocator to Rust.
2017-02-02 10:55:35 +00:00
f512ea42dc
drtio: initialize si5324 in firmware
2017-02-02 18:11:24 +08:00
whitequark
b95db4fa4e
Use four ethmac buffers instead of two.
...
This should address an issue where the host sends a packet burst,
the second packet in a burst gets dropped, the rest also gets
dropped since smoltcp doesn't do reassembly, and the entire dance
is repeated on every retransmit.
2017-01-30 07:42:27 +00:00
9800acea92
drtio: program Si5324 for 150MHz in 3G config
2017-01-30 14:50:12 +08:00
7daab07a29
drtio: fix syntax/import
2017-01-30 13:01:45 +08:00
d8e9949266
drtio: initialize AD9516 clock chip
2017-01-30 11:06:45 +08:00
f6024b6c9a
drtio: fix ad9154 extension registration
2017-01-30 10:59:22 +08:00
43aad0914e
python3.5 -> python3
...
Many things also work with Python 3.6.
2017-01-30 09:24:43 +08:00
94b0783897
drtio: remove support for transceiver SMAs
...
Passive SFP cables do not require bitstream rebuilds and do not cause weird transceiver failures.
2017-01-27 23:33:50 +08:00
whitequark
de17908b38
Revert "Globally update UART baudrate to 921600."
...
This reverts commit b29e2d5bfe
2017-01-25 00:31:28 +00:00
whitequark
b29e2d5bfe
Globally update UART baudrate to 921600.
2017-01-24 22:25:58 +00:00
28a41a2f60
gateware: fix aeb1ba847
2017-01-18 17:11:02 -06:00
ce31ffddb0
firmware: add satellite manager
...
The code duplication with the runtime should be cleaned up later.
2017-01-18 16:50:32 -06:00
b40953800a
gateware: soc -> amp.soc
2017-01-18 15:28:14 -06:00
b8d89d56b1
drtio: add GenericRXSynchronizer
2017-01-15 13:44:43 -06:00
f75fffcf96
drtio: fix satellite RX data corruption
2017-01-10 14:29:30 -06:00
fe53bab953
targets: kc705 -> kc705_dds
2017-01-05 18:40:56 +01:00
082fdaf450
move i2c to libboard, do bit-banging on comms CPU
2017-01-04 21:04:38 +01:00
c08fc8aae9
firmware: support moninj without DDS. Closes #650
2017-01-04 11:26:02 +01:00
455250b3f9
remove DDS_AD9914 and DDS_ONEHOT_SEL
2017-01-03 22:04:25 +01:00
7ff77bceac
move AD9616 and AD9154 initialization to firmware
2017-01-03 16:11:38 +01:00
417708af90
phaser: add note about DDS defines ( #650 )
2017-01-02 22:15:21 +01:00
61abd994e9
Revert "fir: force dsp48"
...
This reverts commit 0ad433832d1b6dcd803ffa086ae73b2ee0568326.
2016-12-14 19:16:07 +01:00
641d109786
fir: force dsp48
2016-12-14 19:16:07 +01:00
527757b471
kc705_drtio: use ad9154_fmc_ebz
2016-12-13 14:30:26 +08:00
03d13d3811
phaser: dma/drtio changes
2016-12-12 17:46:36 +01:00
c63fa46430
Merge branch 'phaser2'
...
* phaser2: (157 commits)
sawg/hbf: tweak pipeline for timing
fir: register multiplier output
conda/phaser: build-depend on numpy
sawg: reduce coefficient width
sawg: fix latency
test/fir: needs mpl. don't run by default
test/sawg: patch spline
sawg: use ParallelHBFCascade to AA [WIP]
fir: add ParallelHBFCascade
fir: add ParallelFIR and test
gateware/dsp: add FIR and test
README_PHASER: update
sawg: documentation
sawg: extract spline
sawg: document
sawg: demo_2tone
sawg: round to int64
gateware/phaser -> gateware/ad9154_fmc_ebz
phaser: fix typo
sawg: merge set/set64
...
2016-12-12 17:31:39 +01:00
0a9f69a3ed
kc705_drtio_master: add missing rtio_core CSRs
2016-12-09 19:23:36 +08:00
bc36bda94a
perform RTIO init on comms CPU side
2016-12-09 14:16:55 +08:00
b311830fc4
kc705: fix drtio_aux address conflict
2016-12-06 18:28:48 +08:00
4669d3f02f
kc705_drtio_satellite: add MiSoC system, hook up auxiliary controller
2016-12-06 14:56:42 +08:00
f4b7d39a69
kc705_drtio_master: hook up auxiliary controller
2016-12-06 14:56:15 +08:00
5d145ff912
drtio: add false paths between sys and transceiver clocks
2016-12-03 23:03:01 +08:00
4b97b9f8ce
drtio: add clock constraints
2016-12-03 22:17:29 +08:00
cbf1004df3
gateware/phaser -> gateware/ad9154_fmc_ebz
2016-12-02 14:11:41 +01:00
6353f6d590
drtio: support different configurations and speeds
2016-12-02 17:22:22 +08:00
d4cb1eb998
kc705: integrate DMA
2016-12-01 16:31:00 +08:00
27160f5912
phaser: make sysref input only for timing
2016-11-29 15:28:10 +01:00
cf342eca6e
kc705_drtio_master: fix number of fine RTIO timestamp bits
2016-11-29 10:44:27 +08:00
f4c6d6eb69
kc705_drtio_master: fix number of fine RTIO timestamp bits
2016-11-28 15:18:54 +08:00
85f2467e2c
rtio: fix RTIO/DRTIO timestamp resolution discrepancy
2016-11-28 15:01:46 +08:00
9fdd29ddae
drtio: connect KernelInitiator correctly
2016-11-28 14:36:18 +08:00
c419c422fa
drtio: support for local RTIO core
2016-11-28 14:33:26 +08:00
55e37b41ec
phaser: use ttl_simple.Input for sync
2016-11-24 15:55:26 +01:00
8060652913
phaser: use Inout_8X
2016-11-24 15:21:03 +01:00
617650f3b2
phaser: extract target
2016-11-24 15:20:51 +01:00
32fdacd95a
Merge remote-tracking branch 'm-labs/master' into phaser2
...
* m-labs/master:
runtime: don't attempt to perform writeback if disabled in kernel.
runtime: print trace level log messages to UART during startup.
runtime: support for targets without RTIO log channel
runtime: support for targets without I2C
kc705: remove stale DDS definition
runtime: show a prompt to erase startup/idle kernels.
2016-11-23 14:56:29 +01:00
0443f83d5e
runtime: support for targets without RTIO log channel
2016-11-23 10:50:55 +08:00
0c49679984
runtime: support for targets without RTIO log channel
2016-11-23 10:48:26 +08:00
fbd83cf9ee
kc705: remove stale DDS definition
2016-11-22 22:48:22 +08:00
9acc7d135e
gateware: common RTIO interface
2016-11-22 22:46:50 +08:00
0aaf120ca7
kc705: remove stale DDS definition
2016-11-22 22:46:19 +08:00
3459793586
Merge branch 'master' into drtio
2016-11-22 15:15:22 +08:00
4160490e0a
Merge branch 'phaser' into phaser2
...
* phaser: (23 commits)
RELEASE_NOTES: update
pipistrello: add some inputs
Remove last vestiges of nist_qc1.
Fully drop AD9858 and kc705-nist_qc1 support (closes #576 ).
coredevice.dds: reimplement fully in ARTIQ Python.
compiler: unbreak casts to int32/int64.
analyses.constness: fix false positive on x[...].
inferencer: significantly improve the op-assignment diagnostic.
Fix tests.
Move mu_to_seconds, seconds_to_mu to Core.
artiq_devtool: don't crash on invalid utf-8.
artiq_devtool: detect a race condition during connect.
llvm_ir_generator: handle no-op coercions.
conda: use development version of migen/misoc
Revert accidentally committed code.
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
analyses.invariant_detection: implement (#622 ).
Fix whitespace.
coredevice.dds: work around the round(numpy.float64()) snafu.
coredevice.dds: update from obsolete int(width=) syntax (fixes #621 ).
...
2016-11-21 17:29:46 +01:00
f7e8961ab0
Merge branch 'master' into phaser
...
* master: (23 commits)
RELEASE_NOTES: update
pipistrello: add some inputs
Remove last vestiges of nist_qc1.
Fully drop AD9858 and kc705-nist_qc1 support (closes #576 ).
coredevice.dds: reimplement fully in ARTIQ Python.
compiler: unbreak casts to int32/int64.
analyses.constness: fix false positive on x[...].
inferencer: significantly improve the op-assignment diagnostic.
Fix tests.
Move mu_to_seconds, seconds_to_mu to Core.
artiq_devtool: don't crash on invalid utf-8.
artiq_devtool: detect a race condition during connect.
llvm_ir_generator: handle no-op coercions.
conda: use development version of migen/misoc
Revert accidentally committed code.
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
analyses.invariant_detection: implement (#622 ).
Fix whitespace.
coredevice.dds: work around the round(numpy.float64()) snafu.
coredevice.dds: update from obsolete int(width=) syntax (fixes #621 ).
...
2016-11-21 17:29:39 +01:00
93c310dfa5
pipistrello: add some inputs
2016-11-21 23:43:41 +08:00
whitequark
6aa5d9f6c6
Remove last vestiges of nist_qc1.
2016-11-21 15:36:22 +00:00
whitequark
5e8888d5f3
Fully drop AD9858 and kc705-nist_qc1 support ( closes #576 ).
2016-11-21 15:14:17 +00:00
whitequark
f4b7666768
coredevice.dds: reimplement fully in ARTIQ Python.
...
This commit also drops AD9858 support from software.
2016-11-21 15:13:26 +00:00
174c4be218
phaser: false paths sys<->{jesd,phy.tx}
2016-11-21 09:57:33 +01:00
ad1049d59a
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
...
This reverts commit 4a62e09bd4
2016-11-20 21:35:07 +08:00
whitequark
30598720f4
Fix whitespace.
2016-11-20 09:50:00 +00:00
David Leibrandt
4a62e09bd4
gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623
2016-11-20 15:22:32 +08:00
b714137f76
phaser: 150 MHz rtio/jesd clock
2016-11-19 13:16:30 +01:00
2e482505c6
phaser: fix DDS dummy cfg
2016-11-13 17:08:59 +01:00
aedb6747f2
Merge branch 'master' into phaser
...
* master: (47 commits)
runtime: disable the Nagle algorithm entirely.
runtime: buffer RPC send packets.
runtime: don't print debug messages to the UART.
runtime: print microsecond timestamps in debug messages.
artiq_devtool: abort if build failed.
conda: bump llvmlite-artiq dep.
conda: bump llvmlite-artiq dep.
llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
artiq_devtool: more robust port forwarding.
setup: remove paramiko dependency (optional and developer-only)
artiq_devtool: implement.
artiq_compile: actually disable attribute writeback.
conda: use pythonparser 1.0.
conda: tighten pythonparser dependency (fixes #600 ).
doc: clarify kernel_invariant doc (fixes #609 ).
compiler: Emit all-kernel_invariant objects as LLVM constants
conda: update for LLVM 3.9.
add has_dds, use config flags
Revert "Revert "Revert "Revert "Update for LLVM 3.9.""""
Revert "Revert "Revert "Update for LLVM 3.9."""
...
2016-11-13 16:54:28 +01:00
99ad9b5917
add has_dds, use config flags
2016-11-08 23:33:03 +08:00
d158c69be0
phaser: fix frequency comment
2016-11-05 16:54:23 +01:00
47b9868c68
kc705_drtio_master: pretend drtio is rtio
2016-11-05 23:48:29 +08:00
de065b7578
kc705_drtio_satellite: set output dir
2016-11-05 23:48:15 +08:00
whitequark
00100148f1
Si5324: actually write value of N32 into registers.
2016-11-02 07:09:04 +00:00
1ed3278783
remove stale TODO
2016-11-02 10:53:54 +08:00
whitequark
a6ae254796
Si5324: update to free run from XA/XB, with CKIN1 having priority.
2016-11-01 16:01:24 +00:00
07ad00c1ca
drtio: split kernel/system CSRs
2016-10-31 18:09:36 +08:00
9aa94e1a2d
adapt to migen/misoc changes
2016-10-31 00:53:01 +08:00
2392113bb6
kc705: use misoc clock for false path
2016-10-30 11:16:04 +08:00
c656a53532
kc705: clean up clock constraints
2016-10-29 21:28:01 +08:00
ed4d57c638
use new Migen signal attribute API
2016-10-29 21:19:58 +08:00
da5208e160
drtio: add master gateware target
2016-10-29 17:31:15 +08:00
2a1e529dcf
phaser: DDS config dummies
2016-10-28 01:58:08 +02:00
c428800caf
phaser: spi, sma_gpio: 2.5 V
2016-10-27 15:53:49 +02:00
e7dbed3b02
gateware: KC705 satellite target
2016-10-17 19:23:45 +08:00
Florent Kermarrec
0259c80015
phaser/kc705: remove transceiver initialization workaround
2016-10-14 19:06:43 +02:00
b41b9de905
phaser: tag jesd as clock net
2016-10-14 10:46:33 +02:00
4ea3dea217
phaser: broad spectrum antibiotics with xilinx false paths
2016-10-14 10:22:03 +02:00
e400f8d672
phaser: add two more registers before jesd
2016-10-14 09:54:56 +02:00
3c9c42c779
phaser: drive rtio from jesd-bufg
2016-10-14 02:26:19 +02:00
808874a523
phaser: drive cd_jesd with BUFG
2016-10-14 01:57:48 +02:00
342d6d756e
phaser: bypass gtx phalign
2016-10-14 00:59:53 +02:00
89150c9817
phaser: 10G line rate
2016-10-14 00:53:38 +02:00
42c6658ffe
phaser: add some more blinking leds
2016-10-13 15:21:27 +02:00
6a456bd7d4
phaser: feed correct sink (crucial)
2016-10-13 15:17:38 +02:00
c8e45ae3f6
phaser: cleanup jesd phy instantiation a bit
2016-10-13 14:43:24 +02:00
78a41eec8f
phaser: kc705: syntax
2016-10-13 12:38:32 +02:00
Florent Kermarrec
af0e8582a2
phaser: use new jesd clocking
2016-10-13 11:51:06 +02:00
1117fe191b
phaser: support core stpl
2016-10-12 12:03:29 +02:00
f515c11f26
phaser: fix refclk period spec
2016-10-11 20:13:34 +02:00
bae5b73155
phaser: comment out stpl test
2016-10-11 19:50:19 +02:00
2b1cca2e7e
phaser: stpl
2016-10-11 19:29:27 +02:00
18d18b6685
phaser: add sync ttl input for monitoring
2016-10-10 17:13:23 +02:00
Florent Kermarrec
c08caae171
phaser: use qpll
2016-10-10 17:05:42 +02:00
9b860b26e8
phaser: fix rtio pll inputs
2016-10-07 13:00:42 +02:00
09434ec054
phaser: also adapt rtio_crg
2016-10-07 12:44:22 +02:00
Florent Kermarrec
b02a7234f6
phaser: use 125MHz refclk for jesd
2016-10-07 08:59:34 +02:00
1193ba4bf4
ad9154: merge csr spaces
2016-10-06 16:21:15 +02:00
4d87f0e9e0
phaser: instantiate jesd204b core, wire up
2016-10-06 14:44:22 +02:00
4a0eaf0f95
phaser: add jesd204b rtio dds
...
gateware: add jesd204b awg
gateware: copy phaser (df3825a)
dsp/tools: update satadd mixin
phaser: no DDS stubs
dsp: accu fix
phaser: cleanup/reduce
sawg: kernel support and docs
sawg: coredevice api fixes
sawg: example ddb/experiment
phaser: add conda package
examples/phaser: typo
sawg: adapt tests, fix accu stb
sawg: tweak dds parameters
sawg: move/adapt/extend tests
sawg: test phy, refactor
phaser: non-rtio spi
phaser: target cli update
phaser: ad9154-fmc-ebz pins
phaser: reorganize fmc signal naming
phaser: add test mode stubs
phaser: txen is LVTTL
phaser: clk spi xfer test
phaser: spi for ad9154 and ad9516
phaser: spi tweaks
ad9154: add register map from ad9144.xml
ad9516: add register map from ad9517.xml and manual adaptation
ad9154_reg: just generate getter/setter macros as well
ad9154: reg WIP
ad9154: check and fix registers
kc705: single ended rtio_external_clk
use single ended user_sma_clk_n instead of p/n to free up one clock sma
kc705: mirror clk200 at user_sma_clock_p
ad9516_regs.h: fix B_COUNTER_MSB
phase: wire up clocking differently
needs patched misoc
kc705: feed rtio_external_clock directly
kc705: remove rtio_external_clk for phaser
phaser: spi tweaks
ad9516: some startup
ad9516_reg fixes
phaser: setup ad9516 for supposed 500 MHz operation
ad9516: use full duplex spi
ad9154_reg: add CONFIG_REG_2
ad9154_reg: fixes
phaser: write some ad9154 config
ad9154_reg: fixes
ad9154: more init, and human readable setup
ad9154/ad9516: merge spi support
ad9154: status readout
Revert "kc705: remove rtio_external_clk for phaser"
This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366.
Revert "kc705: feed rtio_external_clock directly"
This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5.
Revert "phase: wire up clocking differently"
This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc.
Revert "kc705: mirror clk200 at user_sma_clock_p"
This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba.
Revert "kc705: single ended rtio_external_clk"
This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf.
ad9516: 2000 MHz clock
phaser: test clock dist
phaser: test freqs
ad9154: iostandards
phaser: drop clock monitor
phaser: no separate i2c
phaser: drive rtio from refclk, wire up sysref
phaser: ttl channel for sync
ad9154: 4x interp, status, tweaks
phaser: sync/sysref 33V banks
phaser: sync/sysref LVDS_25 inputs are VCCO tolerant
phaser: user input-only ttls
phaser: rtio fully from refclk
ad9154: reg name usage fix
ad9154: check register modifications
Revert "ad9154: check register modifications"
This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564.
ad9154: fix status code
ad9154: addrinc, recal serdes pll
phaser: coredevice, example tweaks
sawg: missing import
sawg: type fixes
ad9514: move setup functions
ad9154: msb first also decreasing addr
phaser: use sys4x for rtio internal ref
phaser: move init code to main
phaser: naming cleanup
phaser: cleanup pins
phaser: move spi to kernel cpu
phaser: kernel support for ad9154 spi
ad9154: add r/w methods
ad9154: need return annotations
ad9154: r/w methods are kernels
ad9154_reg: portable helpers
phaser: cleanup startup kernel
ad9154: status test
ad9154: prbs test
ad9154: move setup, document
phaser: more documentation
2016-10-05 16:17:50 +02:00
8280e72e90
gateware: use new misoc CSR mapping API
2016-09-24 20:48:37 +08:00
2bb90a4449
pipistrello: shrink a few more fifos
2016-09-21 02:29:05 +02:00
454b48df97
pipistrello: shrink fifos a bit more to relax pnr
2016-07-23 12:55:49 +02:00
8cb29fcb3b
targets/kc705: redefine user SMAs as 3.3V IO. Closes #502
2016-07-07 14:53:01 +08:00
dhslichter
141edb521a
qc2: swap SPI/TTL, all TTL lines are now In+Out compatible
2016-05-19 10:42:03 +08:00
9707981c07
targets/kc705: fix default -H option
2016-04-30 00:30:24 +08:00
dhslichter
f395a630e0
Updated qc2 pinouts for SPI and 2x DDS bus, update docs
2016-04-13 18:38:34 +08:00
ed1c368e73
gateware: name targets consistently. Closes #290
2016-04-05 16:07:29 +08:00
8f54a1e619
pipistrello: sys_clk 83 -> 75 MHz
...
This should close #341 once migen generates stable output.
2016-03-21 13:47:32 +01:00
0e1f75ec49
targets/kc705/qc2: hook up HPC backplane
2016-03-16 16:19:56 +08:00
f0b0b1bac7
support for multiple DDS buses (untested)
2016-03-09 17:12:50 +08:00
f33baf339f
pipistrello: drop ttls on pmod, add leds back in
2016-03-08 23:34:51 +01:00
f39208c95a
pipistrello: try with fewer leds/pmod ttl
2016-03-08 22:10:47 +01:00
0d431cb019
pipistrello: make pmod extension header, cleanup
2016-03-08 17:07:44 +01:00
a8fe3f50c3
pipistrello: grow fifos a bit (may make ise happier)
2016-03-08 16:17:37 +01:00
00d4775da5
pipistrello: shrink fifos a bit (may make ise happier)
2016-03-08 15:40:12 +01:00
9c11cda7dc
pipistrello: use ttl_simple for pmod[4:8]
2016-03-08 13:52:52 +01:00
104d641c59
pipistrello: move the spi channel like kc705
2016-03-08 13:30:05 +01:00
2180c5af7c
pipistrello: make pmod[4:8] available as ttls
2016-03-08 13:07:58 +01:00
e809e89571
pipistrello: adhere to pmod interface type 2 layout
2016-03-08 13:01:52 +01:00
e8b59b00f6
soc: use add_extra_software_packages, factor builder code
2016-03-07 00:18:47 +08:00
a8a74d7840
targets/kc705: enable I2C for all hardware adapters
2016-03-05 00:19:59 +08:00
7ff0c89d51
kc705.clock: add all spi buses
2016-03-04 00:03:48 +01:00
423ca03f3b
runtime: bit-banged i2c support (untested)
2016-03-03 17:46:42 +08:00
cfe72c72a2
gateware/kc705: add I2C GPIO core for QC2
2016-03-03 15:32:10 +08:00
a901971e58
gateware/soc: factor code to connect CSR device to kernel CPU
2016-03-03 15:12:15 +08:00
9af12230c8
soc: add timer to kernel CPU system
2016-03-03 13:19:17 +08:00
d3f36ce784
kc705: add false paths for ethernet phy
...
* vivado prefers rsys_clk over sys_clk (despite the assignment hierarchy)
(We need DONT_TOUCH and/or KEEP verilog annotations to fix this)
2016-03-02 19:56:24 +01:00
2cc1dfaee3
kc705: move ttl channels together again, update doc
2016-03-01 19:40:32 +01:00
f2ec8692c0
nist_clock: disable spi1/2
2016-03-01 01:52:46 +01:00
7ef21f03b9
nist_clock: add SPIMasters to spi buses
2016-02-29 22:19:39 +01:00
7ab7f7d75d
Merge branch 'master' into spimaster
...
* master:
artiq_flash: use term 'gateware'
targets/kc705-nist_clock: add clock generator on LA32 for testing purposes
doc: insist that output() must be called on TTLInOut. Closes #297
doc: update install instructions
coredevice: do not give up on UTF-8 errors in log. Closes #300
use m-labs setup for defaults
fix indentation
2016-02-29 20:47:52 +01:00
5fad570f5e
targets/kc705-nist_clock: add clock generator on LA32 for testing purposes
2016-03-01 00:35:26 +08:00
572c49f475
use m-labs setup for defaults
2016-02-29 21:35:23 +08:00
ad34927b0a
spi: RTIO_SPI_CHANNEL -> RTIO_FIRST_SPI_CHANNEL
2016-02-29 11:35:49 +01:00
8d7e92ebae
pipistrello: set RTIO_SPI_CHANNEL
2016-02-29 00:37:00 +01:00
d5893d15fb
gateware.kc705: make xadc/ams an extension header
2016-02-28 22:41:17 +01:00
312e09150e
kc705/clock: add spi bus for dac on ams101
2016-02-28 21:17:53 +01:00
ade3eda19a
gateware.pipistrello: use pmod for spi
2016-02-27 11:29:40 +01:00
fb929c8599
gateware/spi: stubs
2016-02-26 13:11:10 +01:00
a8545fc1f7
targets/kc705: set up user_sma_gpio_n like other TTLs
2016-02-22 22:35:15 +08:00
4946a53456
Revert "targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance"
...
This reverts commit 04b0db1a91
2016-02-22 17:52:40 +08:00
d1119d7747
artiq_dir: move out of tools to unlink dependencies
2016-01-25 18:15:50 -07:00
2832d200f2
Merge remote-tracking branch 'm-labs/master' into ppp2
...
* m-labs/master:
test/worker: update
gui/log: display level and date information in tooltips
master: add filename in worker log entries. Closes #226
master: finer control of worker exception reporting. Closes #233
conda: add artiq-kc705-nist_clock
gateware: add QC1 docstring
gateware: add clock target from David
gateware: clean up and integrate QC2 modifications from Daniel
add information about CLOCK hardware
2016-01-25 12:17:04 -07:00
