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https://github.com/m-labs/artiq.git
synced 2024-12-25 11:18:27 +08:00
kasli: generate fine RTIO clock in DRTIO targets, separate RTIO channel code
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parent
e65e2421a3
commit
caf7b14b55
@ -379,7 +379,32 @@ class SYSU(_StandaloneBase):
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self.add_rtio(rtio_channels)
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class Master(MiniSoC, AMPSoC):
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class _RTIOClockMultiplier(Module):
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def __init__(self, rtio_clk_freq):
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# See "Global Clock Network Deskew Using Two BUFGs" in ug472.
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clkfbout = Signal()
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clkfbin = Signal()
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rtiox4_clk = Signal()
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self.specials += [
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio"),
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i_RST=ResetSignal("rtio"),
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p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
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o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
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p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
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),
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Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk)
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]
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class _MasterBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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@ -412,8 +437,8 @@ class Master(MiniSoC, AMPSoC):
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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sfp_ctl = [platform.request("sfp_ctl", i) for i in range(1, 3)]
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self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctl]
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self.sfp_ctl = [platform.request("sfp_ctl", i) for i in range(1, 3)]
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self.comb += [sc.tx_disable.eq(0) for sc in self.sfp_ctl]
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self.submodules.drtio_transceiver = gtp_7series.GTP(
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qpll_channel=self.drtio_qpll_channel,
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data_pads=[platform.request("sfp", i) for i in range(1, 3)],
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@ -425,7 +450,7 @@ class Master(MiniSoC, AMPSoC):
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drtio_csr_group = []
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drtio_memory_group = []
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drtio_cri = []
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self.drtio_cri = []
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for i in range(2):
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core_name = "drtio" + str(i)
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memory_name = "drtio" + str(i) + "_aux"
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@ -435,7 +460,7 @@ class Master(MiniSoC, AMPSoC):
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core = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})(
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DRTIOMaster(self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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drtio_cri.append(core.cri)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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memory_address = self.mem_map["drtio_aux"] + 0x800*i
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@ -454,18 +479,9 @@ class Master(MiniSoC, AMPSoC):
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self.crg.cd_sys.clk,
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gtp.txoutclk, gtp.rxoutclk)
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rtio_channels = []
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phy = ttl_simple.Output(platform.request("user_led", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for sc in sfp_ctl:
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phy = ttl_simple.Output(sc.led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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@ -479,7 +495,7 @@ class Master(MiniSoC, AMPSoC):
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri] + drtio_cri)
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[self.rtio_core.cri] + self.drtio_cri)
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_analyzer = rtio.Analyzer(self.cri_con.switch.slave,
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@ -519,7 +535,7 @@ class Master(MiniSoC, AMPSoC):
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self.drtio_qpll_channel, self.ethphy_qpll_channel = qpll.channels
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class Satellite(BaseSoC):
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class _SatelliteBase(BaseSoC):
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mem_map = {
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"drtio_aux": 0x50000000,
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}
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@ -536,18 +552,6 @@ class Satellite(BaseSoC):
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platform = self.platform
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rtio_clk_freq = 150e6
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rtio_channels = []
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phy = ttl_simple.Output(platform.request("user_led", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(1, 3):
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phy = ttl_simple.Output(platform.request("sfp_ctl", i).led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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disable_si5324_ibuf = Signal(reset=1)
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disable_si5324_ibuf.attr.add("no_retiming")
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si5324_clkout = platform.request("si5324_clkout")
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@ -574,19 +578,6 @@ class Satellite(BaseSoC):
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self.sync += disable_si5324_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.drtio_transceiver.channels[0], rtio_channels,
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self.rx_synchronizer))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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@ -608,6 +599,80 @@ class Satellite(BaseSoC):
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self.crg.cd_sys.clk,
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gtp.txoutclk, gtp.rxoutclk)
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self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.drtio_transceiver.channels[0], rtio_channels,
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self.rx_synchronizer))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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class Master(_MasterBase):
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def __init__(self, *args, **kwargs):
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_MasterBase.__init__(self, *args, **kwargs)
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platform = self.platform
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platform.add_extension(_dio("eem0"))
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rtio_channels = []
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phy = ttl_simple.Output(platform.request("user_led", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for sc in self.sfp_ctl:
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phy = ttl_simple.Output(sc.led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(8):
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pads = platform.request("eem0", i)
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phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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class Satellite(_SatelliteBase):
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def __init__(self, *args, **kwargs):
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_SatelliteBase.__init__(self, *args, **kwargs)
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platform = self.platform
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platform.add_extension(_dio("eem0"))
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rtio_channels = []
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phy = ttl_simple.Output(platform.request("user_led", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(1, 3):
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phy = ttl_simple.Output(platform.request("sfp_ctl", i).led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(8):
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pads = platform.request("eem0", i)
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phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_rtio(rtio_channels)
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def main():
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parser = argparse.ArgumentParser(
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