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artiq/artiq/gateware/targets
Sebastien Bourdeauducq fc3d97f1f7 drtio: remove spurious multichannel transceiver clock constraints
They used to cause (otherwise harmless) Vivado critical warnings.
2018-03-09 22:46:27 +08:00
..
__init__.py package everything to rebuild core device binaries 2015-11-09 10:47:14 +08:00
kasli.py drtio: remove spurious multichannel transceiver clock constraints 2018-03-09 22:46:27 +08:00
kc705.py kc705: switch backplane spi to spi2 2018-03-01 11:19:18 +01:00
sayma_amc.py drtio: remove spurious multichannel transceiver clock constraints 2018-03-09 22:46:27 +08:00
sayma_rtm.py firmware, sayma: port converter_spi to spi2 2018-03-01 11:19:18 +01:00