gateware: add AD5360 monitor (untested)

artiq/gateware/rtio/phy/ad5360_monitor.py

@@ -0,0 +1,48 @@
+from migen import *
+
+from artiq.coredevice.spi import SPI_XFER_ADDR, SPI_DATA_ADDR
+from artiq.coredevice.ad5360 import _AD5360_CMD_DATA, _AD5360_WRITE_CHANNEL
+
+
+class AD5360Monitor(Module):
+    def __init__(self, spi_rtlink, ldac_rtlink=None, cs_no=0, cs_onehot=False, nchannels=32):
+        self.probes = [Signal(16) for i in range(nchannels)]
+
+        if ldac_rtlink is None:
+            write_targets = self.probes
+        else:
+            write_targets = [Signal(16) for i in range(nchannels)]
+
+            ldac_oif = ldac_rtlink.o
+            if hasattr(ldac_oif, "address"):
+                ttl_level_adr = ldac_oif.address == 0
+            else:
+                ttl_level_adr = 1
+            self.sync.rio_phy += \
+                If(ldac_oif.stb & ttl_level_adr & ~ldac_oif.data[0],
+                    [probe.eq(write_target) for probe, write_target in zip(self.probes, write_targets)]
+                )
+        
+        spi_oif = spi_rtlink.o
+
+        selected = Signal()
+        if cs_onehot:
+            self.sync.rio_phy += [
+                If(spi_oif.stb & (spi_oif.address == SPI_XFER_ADDR),
+                    selected.eq(spi_oif.data[cs_no])
+                )
+            ]
+        else:
+            self.sync.rio_phy += [
+                If(spi_oif.stb & (spi_oif.address == SPI_XFER_ADDR),
+                    selected.eq(spi_oif.data[:16] == cs_no)
+                )
+            ]
+
+        writes = {_AD5360_CMD_DATA | _AD5360_WRITE_CHANNEL(i): t.eq(spi_oif.data[8:24])
+                  for i, t in enumerate(write_targets)}
+        self.sync.rio_phy += [
+            If(spi_oif.stb & (spi_oif.address == SPI_DATA_ADDR),
+                Case(spi_oif.data[24:], writes)
+            )
+        ]

artiq/gateware/targets/kc705_dds.py

@@ -17,7 +17,7 @@ from misoc.integration.builder import builder_args, builder_argdict
 from artiq.gateware.amp import AMPSoC, build_artiq_soc
 from artiq.gateware import rtio, nist_clock, nist_qc2
 from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
-                                     dds, spi)
+                                     dds, spi, ad5360_monitor)
 from artiq import __version__ as artiq_version
 
 
@@ -259,15 +259,19 @@ class NIST_CLOCK(_NIST_Ions):
         rtio_channels.append(rtio.Channel.from_phy(
             phy, ofifo_depth=4, ififo_depth=4))
 
-        phy = spi.SPIMaster(self.platform.request("zotino_spi_p", 0),
-                            self.platform.request("zotino_spi_n", 0))
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
+        sdac_phy = spi.SPIMaster(self.platform.request("zotino_spi_p", 0),
+                                 self.platform.request("zotino_spi_n", 0))
+        self.submodules += sdac_phy
+        rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4))
 
         pads = platform.request("zotino_ldac")
-        phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy))
+        ldac_phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
+        self.submodules += ldac_phy
+        rtio_channels.append(rtio.Channel.from_phy(ldac_phy))
+
+        dac_monitor = ad5360_monitor.AD5360Monitor(sdac_phy.rtlink, ldac_phy.rtlink)
+        self.submodules += dac_monitor
+        sdac_phy.probes.extend(dac_monitor.probes)
 
         phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
         self.submodules += phy