mirror of https://github.com/m-labs/artiq
opticlock: examples
parent
a3d136d30d
commit
be693bc8a9
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@ -0,0 +1,306 @@
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# This is an example device database that needs to be adapted to your setup.
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# The RTIO channel numbers here are for OPTICLOCK on KASLI.
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# The list of devices here is not exhaustive.
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core_addr = "vettel.ber.quartiq.de"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1e-9}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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"i2c_switch0": {
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"type": "local",
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"module": "artiq.coredevice.i2c",
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"class": "PCA9548",
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"arguments": {"address": 0x70}
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},
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"i2c_switch1": {
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"type": "local",
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"module": "artiq.coredevice.i2c",
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"class": "PCA9548",
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"arguments": {"address": 0x71}
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},
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"ttl0": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 0},
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},
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"ttl1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 1},
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},
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"ttl2": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 2},
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},
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"ttl3": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 3},
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},
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"ttl4": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 4},
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},
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"ttl5": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 5},
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},
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"ttl6": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 6},
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},
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"ttl7": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 7},
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},
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"ttl8": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 8},
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},
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"ttl9": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 9},
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},
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"ttl10": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 10},
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},
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"ttl11": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 11},
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},
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"ttl12": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 12},
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},
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"ttl13": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 13},
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},
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"ttl14": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 14},
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},
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"ttl15": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 15},
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},
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"ttl16": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 16},
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},
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"ttl17": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 17},
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},
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"ttl18": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 18},
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},
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"ttl19": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 19},
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},
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"ttl20": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 20},
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},
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"ttl21": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 21},
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},
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"ttl22": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 22},
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},
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"ttl23": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 23},
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},
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"spi_novogorny0": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"class": "SPIMaster",
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"arguments": {"channel": 24}
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},
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"ttl_novogorny0_conv": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 25}
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},
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"spi_urukul0": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"class": "SPIMaster",
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"arguments": {"channel": 26}
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},
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"ttl_urukul0_io_update": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 27}
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},
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"ttl_urukul0_sw0": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 28}
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},
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"ttl_urukul0_sw1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 29}
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},
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"ttl_urukul0_sw2": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 30}
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},
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"ttl_urukul0_sw3": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 31}
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},
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"urukul0_cpld": {
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul0",
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"io_update_device": "ttl_urukul0_io_update",
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"refclk": 100e6
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}
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},
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"urukul0_ch0": {
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"type": "local",
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"module": "artiq.coredevice.ad9912",
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"class": "AD9912",
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"arguments": {
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"pll_n": 10,
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"chip_select": 4,
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"cpld_device": "urukul0_cpld",
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"sw_device": "ttl_urukul0_sw0"
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}
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},
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"urukul0_ch1": {
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"type": "local",
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"module": "artiq.coredevice.ad9912",
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"class": "AD9912",
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"arguments": {
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"pll_n": 10,
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"chip_select": 5,
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"cpld_device": "urukul0_cpld",
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"sw_device": "ttl_urukul0_sw1"
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}
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},
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"urukul0_ch2": {
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"type": "local",
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"module": "artiq.coredevice.ad9912",
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"class": "AD9912",
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"arguments": {
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"pll_n": 10,
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"chip_select": 6,
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"cpld_device": "urukul0_cpld",
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"sw_device": "ttl_urukul0_sw2"
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}
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},
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"urukul0_ch3": {
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"type": "local",
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"module": "artiq.coredevice.ad9912",
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"class": "AD9912",
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"arguments": {
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"pll_n": 10,
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"chip_select": 7,
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"cpld_device": "urukul0_cpld",
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"sw_device": "ttl_urukul0_sw3"
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}
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},
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"led0": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 32}
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},
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"led1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 33}
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}
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}
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@ -0,0 +1,21 @@
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from artiq.experiment import *
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class IdleKernel(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("led0")
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@kernel
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def run(self):
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start_time = now_mu() + self.core.seconds_to_mu(500*ms)
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while self.core.get_rtio_counter_mu() < start_time:
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pass
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self.core.reset()
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while True:
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self.led0.pulse(250*ms)
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delay(125*ms)
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self.led0.pulse(125*ms)
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delay(125*ms)
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self.led0.pulse(125*ms)
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delay(250*ms)
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from artiq.experiment import *
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class UrukulTest(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("urukul0_cpld")
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self.setattr_device("urukul0_ch0")
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self.setattr_device("urukul0_ch1")
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self.setattr_device("urukul0_ch2")
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self.setattr_device("urukul0_ch3")
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self.setattr_device("led0")
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def p(self, f, *a):
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print(f % a)
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@kernel
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def run(self):
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self.core.reset()
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self.led0.on()
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delay(5*ms)
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self.led0.off()
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self.urukul0_cpld.init(clk_sel=0)
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self.urukul0_ch0.init()
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self.urukul0_ch1.init()
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self.urukul0_ch2.init()
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self.urukul0_ch3.init()
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delay(1000*us)
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self.urukul0_ch0.set(100*MHz)
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self.urukul0_ch0.sw.on()
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self.urukul0_ch0.set_att(10.)
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delay(1000*us)
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self.urukul0_ch1.set(10*MHz, 0.5)
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self.urukul0_ch1.sw.on()
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self.urukul0_ch1.set_att(0.)
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delay(1000*us)
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self.urukul0_ch2.set(400*MHz)
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self.urukul0_ch2.sw.on()
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self.urukul0_ch2.set_att(0.)
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delay(1000*us)
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self.urukul0_ch3.set(1*MHz)
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self.urukul0_ch3.sw.on()
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self.urukul0_ch3.set_att(20.)
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i = 0
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j = 0
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while True:
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delay(13*us)
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self.urukul0_ch0.write32(0x07, i)
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self.urukul0_cpld.io_update.pulse(10*ns)
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k = self.urukul0_ch0.read32(0x07)
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delay(100*us)
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if k != i:
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#print(i)
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#print(k)
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#if j > 20:
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# return
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j += 1
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#delay(20*ms)
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i += 1
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while True:
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self.urukul0_ch0.sw.pulse(5*ms)
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delay(5*ms)
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while False:
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self.led0.pulse(.5*s)
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delay(.5*s)
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@kernel
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def test_att_noise(self, n=1024):
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bus = self.urukul0_cpld.bus
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bus.set_config_mu(_SPI_CONFIG, _SPIT_ATT_WR, _SPIT_ATT_RD)
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bus.set_xfer(CS_ATT, 32, 0)
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for i in range(n):
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delay(5*us)
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bus.write(self.att_reg)
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bus.set_config_mu(_SPI_CONFIG, _SPIT_DDS_WR, _SPIT_DDS_RD)
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@ -8,6 +8,7 @@ from migen.genlib.cdc import MultiReg
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from migen.build.generic_platform import *
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from migen.build.xilinx.vivado import XilinxVivadoToolchain
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from migen.build.xilinx.ise import XilinxISEToolchain
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from migen.genlib.io import DifferentialOutput
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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@ -231,7 +232,7 @@ class Opticlock(_StandaloneBase):
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platform.add_extension(_dio("eem1"))
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platform.add_extension(_dio("eem2"))
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platform.add_extension(_novogorny("eem3"))
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platform.add_extension(_urukul("eem4", "eem5"))
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platform.add_extension(_urukul("eem5", "eem4"))
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += platform.request("clk_sel").eq(1)
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@ -259,13 +260,16 @@ class Opticlock(_StandaloneBase):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = spi.SPIMaster(self.platform.request("eem4_spi_p"),
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self.platform.request("eem4_spi_n"))
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phy = spi.SPIMaster(self.platform.request("eem5_spi_p"),
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self.platform.request("eem5_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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for signal in "io_update dds_reset sw0 sw1 sw2 sw3".split():
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pads = platform.request("eem4_{}".format(signal))
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pads = platform.request("eem5_dds_reset")
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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for signal in "io_update sw0 sw1 sw2 sw3".split():
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pads = platform.request("eem5_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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