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kc705: port amc101_dac/spi0 and sma_spi to spi2

pull/954/head
Robert Jördens 2018-02-22 10:55:50 +00:00 committed by Robert Jordens
parent 21b1757bfd
commit 771bf87b56
2 changed files with 6 additions and 6 deletions
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4
artiq/examples/kc705_nist_clock/device_db.py
View File

@ -119,7 +119,7 @@ device_db = {
# Generic SPI
"spi0": {
"type": "local",
"module": "artiq.coredevice.spi",
"module": "artiq.coredevice.spi2",
"class": "SPIMaster",
"arguments": {"channel": 23}
},
@ -161,7 +161,7 @@ device_db = {
# DAC
"spi_ams101": {
"type": "local",
"module": "artiq.coredevice.spi",
"module": "artiq.coredevice.spi2",
"class": "SPIMaster",
"arguments": {"channel": 22}
},

8
artiq/gateware/targets/kc705.py
View File

@ -319,7 +319,7 @@ class NIST_CLOCK(_StandaloneBase):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi.SPIMaster(ams101_dac)
phy = spi2.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=4))
@ -423,7 +423,7 @@ class NIST_QC2(_StandaloneBase):
# add clock generators after TTLs
rtio_channels += clock_generators
phy = spi.SPIMaster(ams101_dac)
phy = spi2.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=4))
@ -478,12 +478,12 @@ class SMA_SPI(_StandaloneBase):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi.SPIMaster(ams101_dac)
phy = spi2.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=4))
phy = spi.SPIMaster(self.platform.request("sma_spi"))
phy = spi2.SPIMaster(self.platform.request("sma_spi"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=128))