mirror of https://github.com/m-labs/artiq.git
kasli: fix QPLL instantiation
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@ -287,6 +287,7 @@ class Master(MiniSoC, AMPSoC):
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refclk_div=1)
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qpll = QPLL(self.crg.clk125_buf, qpll_eth_settings,
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si5324_clkout_buf, qpll_drtio_settings)
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self.submodules += qpll
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self.ethphy_qpll_channel, self.drtio_qpll_channel = qpll.channels
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@ -330,6 +331,7 @@ class Satellite(BaseSoC):
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(0, None, si5324_clkout_buf, qpll_drtio_settings)
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self.submodules += qpll
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self.comb += platform.request("sfp_ctl", 0).tx_disable.eq(0)
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self.submodules.transceiver = gtp_7series.GTP(
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