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gateware/targets/sayma_rtm: add dynamic clock mux, cleanup serwb clock constraints
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@ -9,6 +9,7 @@ from migen.build.platforms.sinara import sayma_rtm
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from misoc.interconnect import wishbone, stream
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from misoc.interconnect.csr import *
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from misoc.cores import spi
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from misoc.cores import gpio
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from misoc.integration.wb_slaves import WishboneSlaveManager
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from misoc.integration.cpu_interface import get_csr_csv
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@ -80,12 +81,12 @@ class SaymaRTM(Module):
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self.submodules.rtm_identifier = RTMIdentifier()
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csr_devices.append("rtm_identifier")
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# clock mux: 125MHz ext SMA clock to HMC830 input
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self.comb += [
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platform.request("clk_src_ext_sel").eq(1), # use ext clk from sma
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platform.request("ref_clk_src_sel").eq(1),
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platform.request("dac_clk_src_sel").eq(0), # use clk from dac_clk
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]
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# clock mux: 100MHz ext SMA clock to HMC830 input
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self.submodules.clock_mux = gpio.GPIOOut(Cat(
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platform.request("clk_src_ext_sel"),
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platform.request("ref_clk_src_sel"),
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platform.request("dac_clk_src_sel")))
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csr_devices.append("clock_mux")
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self.comb += [
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platform.request("ad9154_rst_n").eq(1),
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@ -113,9 +114,9 @@ class SaymaRTM(Module):
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serwb_phy_rtm.serdes.cd_serwb_serdes.clk.attr.add("keep")
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serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
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serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
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platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes.clk, 32.0),
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platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk, 1.6),
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platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk, 6.4)
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platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes.clk, 40*1e9/serwb_pll.linerate),
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platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk, 2*1e9/serwb_pll.linerate),
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platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk, 8*1e9/serwb_pll.linerate)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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serwb_phy_rtm.serdes.cd_serwb_serdes.clk,
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