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https://github.com/m-labs/artiq.git
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novogorny: conv -> cnv
* parity with sampler * also add novogorny device to opticlock
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82c4f0eed4
commit
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@ -67,17 +67,17 @@ class Novogorny:
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register.
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:param spi_device: SPI bus device name
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:param conv_device: CONV RTIO TTLOut channel name
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:param cnv_device: CNV RTIO TTLOut channel name
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:param div: SPI clock divider (default: 8)
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:param core_device: Core device name
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"""
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kernel_invariants = {"bus", "core", "conv", "div", "v_ref"}
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kernel_invariants = {"bus", "core", "cnv", "div", "v_ref"}
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def __init__(self, dmgr, spi_device, conv_device, div=8,
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def __init__(self, dmgr, spi_device, cnv_device, div=8,
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core_device="core"):
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self.bus = dmgr.get(spi_device)
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self.core = dmgr.get(core_device)
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self.conv = dmgr.get(conv_device)
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self.cnv = dmgr.get(cnv_device)
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self.div = div
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self.gains = 0x0000
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self.v_ref = 5. # 5 Volt reference
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@ -125,7 +125,7 @@ class Novogorny:
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:param next_ctrl: ADC control word for the next sample
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:return: The ADC result packet (machine units)
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"""
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self.conv.pulse(40*ns) # t_CNVH
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self.cnv.pulse(40*ns) # t_CNVH
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delay(560*ns) # t_CONV max
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_INPUT | spi.SPI_END,
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24, self.div, SPI_CS_ADC)
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@ -163,7 +163,7 @@ class Novogorny:
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24, self.div, SPI_CS_ADC)
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for i in range(len(data)):
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t0 = now_mu()
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self.conv.pulse(40*ns) # t_CNVH
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self.cnv.pulse(40*ns) # t_CNVH
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delay(560*ns) # t_CONV max
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self.bus.write(ctrl << 24)
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at_mu(t0 + dt_mu)
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@ -192,12 +192,21 @@ device_db = {
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"class": "SPIMaster",
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"arguments": {"channel": 24}
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},
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"ttl_novogorny0_conv": {
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"ttl_novogorny0_cnv": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 25}
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},
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"novogorny0" : {
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"type": "local",
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"module": "artiq.coredevice.novogorny",
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"class": "Novogorny",
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"arguments": {
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"spi_device": "spi_novogorny0",
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"cnv_device": "ttl_novogorny0_cnv",
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}
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},
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"spi_urukul0": {
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"type": "local",
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@ -247,7 +247,7 @@ def _novogorny(eem):
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Subsignal("n", Pins(_eem_pin(j, i, "n"))),
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IOStandard("LVDS_25")
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) for i, j, sig in [
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(5, eem, "conv"),
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(5, eem, "cnv"),
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(6, eem, "busy"),
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(7, eem, "scko"),
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]
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@ -369,7 +369,7 @@ class Opticlock(_StandaloneBase):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16))
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for signal in "conv".split():
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for signal in "cnv".split():
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pads = platform.request("eem3_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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