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drtio: remove spurious multichannel transceiver clock constraints
They used to cause (otherwise harmless) Vivado critical warnings.
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parent
caf7b14b55
commit
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@ -472,12 +472,16 @@ class _MasterBase(MiniSoC, AMPSoC):
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self.add_memory_group("drtio_aux", drtio_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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for gtp in self.drtio_transceiver.gtps:
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gtp = self.drtio_transceiver.gtps[0]
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platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gtp.txoutclk, gtp.rxoutclk)
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for gtp in self.drtio_transceiver.gtps[1:]:
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platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gtp.txoutclk, gtp.rxoutclk)
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self.crg.cd_sys.clk, gtp.rxoutclk)
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self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
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@ -330,12 +330,16 @@ class Master(MiniSoC, AMPSoC):
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self.add_memory_group("drtio_aux", drtio_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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for gth in self.drtio_transceiver.gths:
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth.txoutclk, gth.rxoutclk)
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for gth in self.drtio_transceiver.gths[1:]:
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth.txoutclk, gth.rxoutclk)
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self.crg.cd_sys.clk, gth.rxoutclk)
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rtio_channels = []
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for i in range(4):
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