kc705_dds: fix HPC voltages

* VADJ is 3.3 V due to the DDS card on LPC
* the LVDS standards need to be 2.5 V

* the direction control register on HPC (FMC-DIO to VHDCI)
  was LVCMOS33 but while all the LVDS pairs are at VCCIO=VADJ=3.3 V
  they were instantiated as LVDS_25 (ignoring the wrongly powered bank)
* we now use 2.5 V standards on HPC consistently despite VADJ=3.3 V
  and hope for the best.

artiq/gateware/targets/kc705_dds.py

@@ -112,7 +112,7 @@ _zotino = [
         Subsignal("clk", Pins("HPC:LA32_N")),
         Subsignal("ser", Pins("HPC:LA33_P")),
         Subsignal("latch", Pins("HPC:LA32_P")),
-        IOStandard("LVCMOS33")
+        IOStandard("LVCMOS25")
     ),
     ("zotino_spi_p", 0,
         Subsignal("clk", Pins("HPC:LA08_P")),