mirror of https://github.com/m-labs/artiq.git
gateware/targets/sayma_amc: integrate ad9154 correctly (add crg, use cpll instead of qpll, use correct clocking) and cleanup serwb constraints.
This commit is contained in:
Florent Kermarrec
parent
278c739d30
commit
464b24a608
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@ -17,7 +17,7 @@ from misoc.targets.sayma_amc import MiniSoC
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from jesd204b.common import (JESD204BTransportSettings,
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JESD204BPhysicalSettings,
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JESD204BSettings)
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from jesd204b.phy.gth import GTHQuadPLL as JESD204BGTHQuadPLL
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from jesd204b.phy.gth import GTHChannelPLL as JESD204BGTHChannelPLL
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from jesd204b.phy import JESD204BPhyTX
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from jesd204b.core import JESD204BCoreTX
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from jesd204b.core import JESD204BCoreTXControl
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@ -34,21 +34,17 @@ PhyPads = namedtuple("PhyPads", "txp txn")
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to_jesd = ClockDomainsRenamer("jesd")
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class AD9154JESD(Module, AutoCSR):
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class AD9154CRG(Module, AutoCSR):
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linerate = int(6e9)
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refclk_freq = int(150e6)
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fabric_freq = int(125e6)
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def __init__(self, platform):
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self.jreset = CSRStorage(reset=1)
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ps = JESD204BPhysicalSettings(l=8, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=2, k=16, cs=0)
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settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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linerate = 10e9
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refclk_freq = 250e6
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fabric_freq = 125*1000*1000
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self.refclk = Signal()
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refclk2 = Signal()
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self.clock_domains.cd_jesd = ClockDomain()
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refclk_pads = platform.request("dac_refclk")
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refclk_pads = platform.request("dac_refclk", 0)
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self.specials += [
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Instance("IBUFDS_GTE3", i_CEB=0, p_REFCLK_HROW_CK_SEL=0b00,
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@ -58,56 +54,43 @@ class AD9154JESD(Module, AutoCSR):
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AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage),
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]
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self.cd_jesd.clk.attr.add("keep")
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platform.add_period_constraint(self.cd_jesd.clk, 1e9/refclk_freq)
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platform.add_period_constraint(self.cd_jesd.clk, 1e9/self.refclk_freq)
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self.phys = []
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for dac in range(2):
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jesd_pads = platform.request("dac_jesd", dac)
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phys = []
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self.phys.append(phys)
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for i in range(len(jesd_pads.txp)):
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if i % 4 == 0:
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qpll = JESD204BGTHQuadPLL(
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self.refclk, refclk_freq, linerate)
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self.submodules += qpll
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print(qpll) # FIXME
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phy = JESD204BPhyTX(
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qpll, PhyPads(jesd_pads.txp[i], jesd_pads.txn[i]),
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fabric_freq, transceiver="gth")
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phy.transmitter.cd_tx.clk.attr.add("keep")
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platform.add_period_constraint(phy.transmitter.cd_tx.clk,
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40*1e9/linerate)
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platform.add_false_path_constraints(
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# self.crg.cd_sys.clk, FIXME?
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self.cd_jesd.clk,
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phy.transmitter.cd_tx.clk)
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phys.append(phy)
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core = to_jesd(JESD204BCoreTX(
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phys, settings, converter_data_width=64))
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setattr(self.submodules, "core{}".format(dac), core)
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control = to_jesd(JESD204BCoreTXControl(core))
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setattr(self.submodules, "control{}".format(dac), control)
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core.register_jsync(platform.request("dac_sync", dac))
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class AD9154JESD(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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ps = JESD204BPhysicalSettings(l=8, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=2, k=16, cs=0)
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settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_pads = platform.request("dac_jesd", dac)
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phys = []
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for i in range(len(jesd_pads.txp)):
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cpll = JESD204BGTHChannelPLL(
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jesd_crg.refclk, jesd_crg.refclk_freq, jesd_crg.linerate)
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self.submodules += cpll
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#print(cpll)
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phy = JESD204BPhyTX(
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cpll, PhyPads(jesd_pads.txp[i], jesd_pads.txn[i]),
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jesd_crg.fabric_freq, transceiver="gth")
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phy.transmitter.cd_tx.clk.attr.add("keep")
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platform.add_period_constraint(phy.transmitter.cd_tx.clk,
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40*1e9/jesd_crg.linerate)
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platform.add_false_path_constraints(
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sys_crg.cd_sys.clk,
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jesd_crg.cd_jesd.clk,
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phy.transmitter.cd_tx.clk)
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phys.append(phy)
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# self.comb += platform.request("user_led", 3).eq(self.core0.jsync)
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# blinking leds for transceiver reset status
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#for i in range(4):
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# counter = Signal(max=fabric_freq)
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# self.comb += platform.request("user_led", 4 + i).eq(counter[-1])
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# sync = getattr(self.sync, "phy{}_tx".format(i))
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# sync += [
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# counter.eq(counter - 1),
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# If(counter == 0,
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# counter.eq(fabric_freq - 1)
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# )
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# ]
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self.submodules.core = core = to_jesd(JESD204BCoreTX(
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phys, settings, converter_data_width=64))
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self.submodules.control = control = to_jesd(JESD204BCoreTXControl(core))
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core.register_jsync(platform.request("dac_sync", dac))
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class AD9154(Module, AutoCSR):
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def __init__(self, platform):
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self.submodules.jesd = AD9154JESD(platform)
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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self.submodules.jesd = AD9154JESD(platform, sys_crg, jesd_crg, dac)
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self.sawgs = [sawg.Channel(width=16, parallelism=8) for i in range(8)]
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self.submodules += self.sawgs
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@ -173,9 +156,9 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
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serwb_phy_amc.serdes.cd_serwb_serdes.clk.attr.add("keep")
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serwb_phy_amc.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
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serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
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platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes.clk, 32.0),
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platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_20x.clk, 1.6),
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platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk, 6.4)
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platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes.clk, 40*1e9/serwb_pll.linerate),
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platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_20x.clk, 2*1e9/serwb_pll.linerate),
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platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk, 8*1e9/serwb_pll.linerate)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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serwb_phy_amc.serdes.cd_serwb_serdes.clk,
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@ -200,10 +183,14 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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if with_sawg:
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self.submodules.ad9154_0 = AD9154(platform)
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self.submodules.ad9154_crg = AD9154CRG(platform)
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self.submodules.ad9154_0 = AD9154(platform, self.crg, self.ad9154_crg, 0)
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self.submodules.ad9154_1 = AD9154(platform, self.crg, self.ad9154_crg, 1)
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self.csr_devices.append("ad9154_crg")
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self.csr_devices.append("ad9154_0")
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self.csr_devices.append("ad9154_1")
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self.config["HAS_AD9154"] = None
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self.add_csr_group("ad9154", ["ad9154_0"])
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self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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for sawg in self.ad9154_0.sawgs
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