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mirror of https://github.com/m-labs/artiq.git synced 2025-02-09 00:53:18 +08:00
artiq/artiq/gateware/targets
Robert Jordens 7e02d8245c kasli: false paths
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
  ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
2018-02-19 13:05:11 +00:00
..
__init__.py package everything to rebuild core device binaries 2015-11-09 10:47:14 +08:00
kasli.py kasli: false paths 2018-02-19 13:05:11 +00:00
kc705.py gateware: use a per-variant subfolder in --output-dir. (fixes #912) 2018-02-06 08:19:01 +00:00
sayma_amc.py sayma: use Xilinx RX synchronizer 2018-02-19 17:49:53 +08:00
sayma_rtm.py sayma: print RTM gateware version 2018-02-15 19:31:58 +08:00