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https://github.com/m-labs/artiq.git
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kasli: add DRTIO targets (no firmware)
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296ac35f5d
commit
aa62e91487
@ -11,13 +11,16 @@ from migen.build.xilinx.ise import XilinxISEToolchain
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.targets.kasli import (MiniSoC, soc_kasli_args,
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soc_kasli_argdict)
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from misoc.cores.a7_gtp import *
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from misoc.targets.kasli import (BaseSoC, MiniSoC,
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soc_kasli_args, soc_kasli_argdict)
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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@ -72,7 +75,7 @@ class _RTIOCRG(Module, AutoCSR):
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]
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class _KasliBase(MiniSoC, AMPSoC):
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class _StandaloneBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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@ -144,12 +147,12 @@ def _dio(eem):
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for i in range(8)]
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class Opticlock(_KasliBase):
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class Opticlock(_StandaloneBase):
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"""
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Opticlock extension variant configuration
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"""
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def __init__(self, **kwargs):
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_KasliBase.__init__(self, **kwargs)
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_StandaloneBase.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(_dio("eem0"))
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@ -182,21 +185,211 @@ class Opticlock(_KasliBase):
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self.add_rtio(rtio_channels)
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class Master(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"drtio_aux": 0x50000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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platform = self.platform
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rtio_clk_freq = 150e6
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.config["SI5324_FREE_RUNNING"] = None
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self.comb += platform.request("sfp_ctl", 1).tx_disable.eq(0)
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self.submodules.transceiver = gtp_7series.GTP(
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qpll_channel=self.drtio_qpll_channel,
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data_pads=[platform.request("sfp", 1)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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DRTIOMaster(self.transceiver.channels[0]))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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rtio_clk_period = 1e9/rtio_clk_freq
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for gtp in self.transceiver.gtps:
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platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gtp.txoutclk, gtp.rxoutclk)
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rtio_channels = []
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phy = ttl_simple.Output(platform.request("user_led", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.Output(platform.request("sfp_ctl", 2).led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(rtio_channels, glbl_fine_ts_width=3)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri, self.drtio0.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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# Never running out of stupid features, GTs on A7 make you pack
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# unrelated transceiver PLLs into one GTPE2_COMMON yourself.
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def create_qpll(self):
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si5324_clkout = self.platform.request("si5324_clkout")
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si5324_clkout_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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o_O=si5324_clkout_buf)
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qpll_eth_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll_drtio_settings = QPLLSettings(
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refclksel=0b010,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(self.crg.clk125_buf, qpll_eth_settings,
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si5324_clkout_buf, qpll_drtio_settings)
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self.ethphy_qpll_channel, self.drtio_qpll_channel = qpll.channels
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class Satellite(BaseSoC):
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mem_map = {
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"drtio_aux": 0x50000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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**kwargs)
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platform = self.platform
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rtio_clk_freq = 150e6
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rtio_channels = []
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phy = ttl_simple.Output(platform.request("user_led", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.Output(platform.request("sfp_ctl", 2).led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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si5324_clkout = platform.request("si5324_clkout")
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si5324_clkout_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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o_O=si5324_clkout_buf)
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qpll_drtio_settings = QPLLSettings(
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refclksel=0b010,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
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self.comb += platform.request("sfp_ctl", 0).tx_disable.eq(0)
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self.submodules.transceiver = gtp_7series.GTP(
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qpll_channel=qpll.channels[0],
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data_pads=[platform.request("sfp", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.transceiver.channels[0], rtio_channels))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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si5324_clkin = platform.request("si5324_clkin")
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self.specials += \
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Instance("OBUFDS",
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i_I=ClockSignal("rtio_rx0"),
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o_O=si5324_clkin.p, o_OB=si5324_clkin.n
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)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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rtio_clk_period = 1e9/rtio_clk_freq
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gtp = self.transceiver.gtps[0]
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platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gtp.txoutclk, gtp.rxoutclk)
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for Kasli systems")
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builder_args(parser)
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soc_kasli_args(parser)
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parser.add_argument("-V", "--variant", default="opticlock",
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help="variant: opticlock "
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help="variant: opticlock/master/satellite "
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"(default: %(default)s)")
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args = parser.parse_args()
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variant = args.variant.lower()
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if variant == "opticlock":
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cls = Opticlock
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elif variant == "master":
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cls = Master
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elif variant == "satellite":
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cls = Satellite
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else:
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raise SystemExit("Invalid hardware adapter string (--variant)")
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raise SystemExit("Invalid variant (-V/--variant)")
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soc = cls(**soc_kasli_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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