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mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 03:08:27 +08:00

drtio: instrument GTH transceiver

This commit is contained in:
Sebastien Bourdeauducq 2017-12-28 15:03:14 +08:00
parent c626456030
commit 6801921fc0
4 changed files with 29 additions and 8 deletions

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@ -8,6 +8,8 @@ from migen.genlib.cdc import MultiReg
from misoc.interconnect.csr import *
from misoc.cores.code_8b10b import Encoder, Decoder
from microscope import *
from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
from artiq.gateware.drtio.transceiver.gth_ultrascale_init import *
@ -34,14 +36,13 @@ class GTHSingle(Module):
# TX generates RTIO clock, init must be in system domain
tx_init = GTHInit(sys_clk_freq, False)
# RX receives restart commands from RTIO domain
rx_init = ClockDomainsRenamer("rtio_tx")(
GTHInit(rtio_clk_freq, True))
rx_init = ClockDomainsRenamer("rtio_tx")(GTHInit(rtio_clk_freq, True))
self.submodules += tx_init, rx_init
pll_lock = Signal()
cpll_lock = Signal()
self.comb += [
tx_init.plllock.eq(pll_lock),
rx_init.plllock.eq(pll_lock)
tx_init.plllock.eq(cpll_lock),
rx_init.plllock.eq(cpll_lock)
]
txdata = Signal(dw)
@ -77,7 +78,7 @@ class GTHSingle(Module):
p_TXOUT_DIV=2,
i_CPLLRESET=0,
i_CPLLPD=0,
o_CPLLLOCK=pll_lock,
o_CPLLLOCK=cpll_lock,
i_CPLLLOCKEN=1,
i_CPLLREFCLKSEL=0b001,
i_TSTIN=2**20-1,
@ -171,6 +172,14 @@ class GTHSingle(Module):
o_GTHTXN=tx_pads.n
)
self.submodules += [
add_probe_single("drtio_gth", "cpll_lock", cpll_lock),
add_probe_single("drtio_gth", "txuserrdy", tx_init.Xxuserrdy),
add_probe_single("drtio_gth", "rxuserrdy", rx_init.Xxuserrdy, clock_domain="rtio_tx"),
add_probe_buffer("drtio_gth", "txdata", txdata, clock_domain="rtio_tx"),
add_probe_buffer("drtio_gth", "rxdata", rxdata, clock_domain="rtio_rx")
]
# tx clocking
tx_reset_deglitched = Signal()
tx_reset_deglitched.attr.add("no_retiming")
@ -178,8 +187,7 @@ class GTHSingle(Module):
self.clock_domains.cd_rtio_tx = ClockDomain()
if mode == "master":
self.specials += \
Instance("BUFG_GT", i_I=self.txoutclk, o_O=self.cd_rtio_tx.clk,
i_DIV=0)
Instance("BUFG_GT", i_I=self.txoutclk, o_O=self.cd_rtio_tx.clk, i_DIV=0)
self.specials += AsyncResetSynchronizer(self.cd_rtio_tx, tx_reset_deglitched)
# rx clocking
@ -207,6 +215,8 @@ class GTHSingle(Module):
rx_init.restart.eq(clock_aligner.restart),
self.rx_ready.eq(clock_aligner.ready)
]
self.submodules += add_probe_single("drtio_gth", "clock_aligner_ready", clock_aligner.ready,
clock_domain="rtio_tx")
class GTH(Module, TransceiverInterface):

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@ -11,6 +11,8 @@ from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
from misoc.integration.builder import builder_args, builder_argdict
from misoc.targets.sayma_amc import MiniSoC
from microscope import *
from artiq.gateware.amp import AMPSoC, build_artiq_soc
from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple
@ -43,6 +45,9 @@ class Master(MiniSoC, AMPSoC):
platform = self.platform
rtio_clk_freq = 150e6
self.submodules += Microscope(platform.request("serial", 1),
self.clk_freq)
# Si5324 used as a free-running oscillator, to avoid dependency on RTM.
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")

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@ -11,6 +11,8 @@ from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
from misoc.integration.builder import *
from misoc.targets.sayma_amc import BaseSoC
from microscope import *
from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple
from artiq.gateware.drtio.transceiver import gth_ultrascale
@ -36,6 +38,9 @@ class Satellite(BaseSoC):
platform = self.platform
rtio_clk_freq = 150e6
self.submodules += Microscope(platform.request("serial", 1),
self.clk_freq)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))

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@ -17,6 +17,7 @@ requirements:
- migen 0.6.dev py35_50+git82b06ee
- misoc 0.8.dev py35_41+gitc69cb371
- jesd204b 0.4
- microscope
- binutils-or1k-linux >=2.27
- llvm-or1k 4.0.1
- llvmlite-artiq 0.20.0