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sayma: allocate all user LEDs to RTIO, make one TTL SMA input

pull/882/merge
Sebastien Bourdeauducq 2017-12-21 19:27:38 +08:00
parent a23251276d
commit 4fbc8772a5
4 changed files with 42 additions and 34 deletions
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32
artiq/examples/sayma/device_db.py
View File

@ -49,65 +49,77 @@ device_db = {
"class": "TTLOut",
"arguments": {"channel": 1}
},
"ttl_sma0": {
"led1": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 2}
},
"ttl_sma1": {
"led1": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 3}
},
"ttl_sma_out": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 4}
},
"ttl_sma_in": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 5}
},
"sawg0": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 4, "parallelism": 4}
"arguments": {"channel_base": 6, "parallelism": 4}
},
"sawg1": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 14, "parallelism": 4}
"arguments": {"channel_base": 16, "parallelism": 4}
},
"sawg2": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 24, "parallelism": 4}
"arguments": {"channel_base": 26, "parallelism": 4}
},
"sawg3": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 34, "parallelism": 4}
"arguments": {"channel_base": 36, "parallelism": 4}
},
"sawg4": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 44, "parallelism": 4}
"arguments": {"channel_base": 46, "parallelism": 4}
},
"sawg5": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 54, "parallelism": 4}
"arguments": {"channel_base": 56, "parallelism": 4}
},
"sawg6": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 64, "parallelism": 4}
"arguments": {"channel_base": 66, "parallelism": 4}
},
"sawg7": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 74, "parallelism": 4}
"arguments": {"channel_base": 76, "parallelism": 4}
},
}

12
artiq/examples/sayma/repository/demo.py
View File

@ -4,7 +4,7 @@ from artiq.experiment import *
class SAWGTest(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("ttl_sma0")
self.setattr_device("ttl_sma_out")
self.setattr_device("sawg0")
self.setattr_device("sawg1")
@ -28,21 +28,21 @@ class SAWGTest(EnvExperiment):
self.sawg1.amplitude1.set(.4)
self.sawg1.frequency0.set(10*MHz)
self.sawg1.phase0.set(0.)
self.ttl_sma0.pulse(200*ns)
self.ttl_sma_out.pulse(200*ns)
self.sawg1.amplitude1.set(.1)
delay(200*ns)
self.sawg1.amplitude1.set(-.4)
self.ttl_sma0.pulse(200*ns)
self.ttl_sma_out.pulse(200*ns)
self.sawg1.amplitude1.set(.4)
delay(200*ns)
self.sawg1.phase0.set(.25)
self.ttl_sma0.pulse(200*ns)
self.ttl_sma_out.pulse(200*ns)
self.sawg1.phase0.set(.5)
delay(200*ns)
self.sawg0.phase0.set(.5)
self.ttl_sma0.pulse(200*ns)
self.ttl_sma_out.pulse(200*ns)
self.sawg1.frequency0.set(30*MHz)
delay(200*ns)
self.sawg1.frequency0.set(10*MHz)
self.sawg1.phase0.set(0.)
self.ttl_sma0.pulse(200*ns)
self.ttl_sma_out.pulse(200*ns)

6
artiq/examples/sayma/repository/demo_2tone.py
View File

@ -5,7 +5,7 @@ class SAWGTestTwoTone(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("led0")
self.setattr_device("ttl_sma0")
self.setattr_device("ttl_sma_out")
self.setattr_device("sawg0")
self.setattr_device("sawg1")
@ -37,7 +37,7 @@ class SAWGTestTwoTone(EnvExperiment):
delay(20*ms)
self.led0.on()
self.ttl_sma0.on()
self.ttl_sma_out.on()
self.sawg0.frequency0.set(10*MHz)
self.sawg0.phase0.set(0.)
self.sawg0.frequency1.set(1*MHz)
@ -58,5 +58,5 @@ class SAWGTestTwoTone(EnvExperiment):
self.sawg1.amplitude1.set(.0)
self.sawg1.amplitude2.set(.0)
self.ttl_sma0.off()
self.ttl_sma_out.off()
self.led0.off()

26
artiq/gateware/targets/sayma_amc_standalone.py
View File

@ -7,7 +7,6 @@ from collections import namedtuple
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from misoc.cores import gpio
from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
from misoc.integration.builder import builder_args, builder_argdict
from misoc.interconnect import stream
@ -126,12 +125,6 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])
self.submodules.leds = gpio.GPIOOut(Cat(
platform.request("user_led", 0),
platform.request("user_led", 1)))
self.csr_devices.append("leds")
# forward RTM UART to second FTDI UART channel
serial_1 = platform.request("serial", 1)
serial_rtm = platform.request("serial_rtm")
@ -167,17 +160,20 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
# RTIO
rtio_channels = []
for i in (2, 3):
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in (0, 1):
sma_io = platform.request("sma_io", i)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
if with_sawg:
self.submodules.ad9154_crg = AD9154CRG(platform)