mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-24 10:54:02 +08:00
refactor targets
This commit is contained in:
parent
5198c224a2
commit
25f3feeda8
@ -19,6 +19,8 @@ Release notes
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* The master now has a ``--name`` argument. If given, the dashboard is labelled
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with this name rather than the server address.
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* ``artiq_flash --adapter`` has been changed to ``artiq_flash --variant``.
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* ``kc705_dds`` has been renamed ``kc705``.
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* the ``-H/--hw-adapter`` option of ``kc705`` has ben renamed ``-V/--variant``.
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3.2
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27
artiq/build_soc.py
Normal file
27
artiq/build_soc.py
Normal file
@ -0,0 +1,27 @@
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import os
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import subprocess
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from misoc.integration.builder import *
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from artiq.gateware.amp import AMPSoC
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from artiq import __artiq_dir__ as artiq_dir
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def build_artiq_soc(soc, argdict):
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firmware_dir = os.path.join(artiq_dir, "firmware")
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builder = Builder(soc, **argdict)
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builder.software_packages = []
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builder.add_software_package("bootloader", os.path.join(firmware_dir, "bootloader"))
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if isinstance(soc, AMPSoC):
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builder.add_software_package("libm")
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builder.add_software_package("libprintf")
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builder.add_software_package("libunwind")
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builder.add_software_package("ksupport", os.path.join(firmware_dir, "ksupport"))
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builder.add_software_package("runtime", os.path.join(firmware_dir, "runtime"))
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else:
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# Assume DRTIO satellite.
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builder.add_software_package("satman", os.path.join(firmware_dir, "satman"))
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try:
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builder.build()
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except subprocess.CalledProcessError as e:
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raise SystemExit("Command {} failed".format(" ".join(e.cmd)))
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@ -29,17 +29,16 @@ def get_argparser():
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verbosity_args(parser)
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parser.add_argument("-t", "--target", metavar="TARGET",
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type=str, default="kc705_dds",
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type=str, default="kc705",
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help="target to build, one of: "
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"kc705_dds kasli sayma_rtm sayma_amc_standalone "
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"sayma_amc_drtio_master sayma_amc_drtio_satellite")
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"kc705 kasli sayma_rtm sayma_amc")
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parser.add_argument("-g", "--build-gateware",
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default=False, action="store_true",
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help="build gateware, not just software")
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parser.add_argument("-H", "--host",
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type=str, default="lab.m-labs.hk",
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help="SSH host where the development board is located")
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parser.add_argument('-b', "--board",
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parser.add_argument("-b", "--board",
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type=str, default="{board_type}-1",
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help="board to connect to on the development SSH host")
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parser.add_argument("-B", "--board-file",
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@ -73,15 +72,11 @@ def main():
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return os.path.join("/tmp", target, *path)
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extra_build_args = []
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if args.target == "kc705_dds":
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if args.target == "kc705":
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board_type, firmware = "kc705", "runtime"
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elif args.target == "sayma_amc_standalone":
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elif args.target == "sayma_amc":
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board_type, firmware = "sayma_amc", "runtime"
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extra_build_args += ["--rtm-csr-csv", build_dir("sayma_rtm_csr.csv", target="sayma_rtm")]
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elif args.target == "sayma_amc_drtio_master":
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board_type, firmware = "sayma_amc", "runtime"
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elif args.target == "sayma_amc_drtio_satellite":
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board_type, firmware = "sayma_amc", "satman"
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elif args.target == "sayma_rtm":
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board_type, firmware = "sayma_rtm", None
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else:
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@ -51,7 +51,7 @@ Prerequisites:
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parser.add_argument("-t", "--target", default="kc705",
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help="target board, default: %(default)s, one of: "
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"kc705 kasli sayma_amc sayma_rtm")
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parser.add_argument("-m", "--variant", default=None,
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parser.add_argument("-V", "--variant", default=None,
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help="board variant")
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parser.add_argument("-I", "--preinit-command", default=[], action="append",
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help="add a pre-initialization OpenOCD command. "
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@ -1 +1 @@
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from artiq.gateware.amp.soc import AMPSoC, build_artiq_soc
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from artiq.gateware.amp.soc import AMPSoC
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@ -1,13 +1,8 @@
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import os
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import subprocess
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from misoc.cores import timer
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from misoc.interconnect import wishbone
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from misoc.integration.builder import *
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from artiq.gateware.amp.kernel_cpu import KernelCPU
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from artiq.gateware.amp.mailbox import Mailbox
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from artiq import __artiq_dir__ as artiq_dir
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class AMPSoC:
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@ -42,19 +37,3 @@ class AMPSoC:
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self.add_csr_region(name,
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self.mem_map[name] | 0x80000000, 32,
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csrs)
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def build_artiq_soc(soc, argdict):
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firmware_dir = os.path.join(artiq_dir, "firmware")
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builder = Builder(soc, **argdict)
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builder.software_packages = []
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builder.add_software_package("libm")
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builder.add_software_package("libprintf")
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builder.add_software_package("libunwind")
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builder.add_software_package("bootloader", os.path.join(firmware_dir, "bootloader"))
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builder.add_software_package("ksupport", os.path.join(firmware_dir, "ksupport"))
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builder.add_software_package("runtime", os.path.join(firmware_dir, "runtime"))
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try:
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builder.build()
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except subprocess.CalledProcessError as e:
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raise SystemExit("Command {} failed".format(" ".join(e.cmd)))
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@ -15,9 +15,10 @@ from misoc.targets.kasli import (MiniSoC, soc_kasli_args,
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soc_kasli_argdict)
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC, build_artiq_soc
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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@ -186,8 +187,8 @@ def main():
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description="ARTIQ device binary builder for Kasli systems")
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builder_args(parser)
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soc_kasli_args(parser)
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parser.add_argument("--variant", default="opticlock",
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help="extension variant setup: opticlock "
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parser.add_argument("-V", "--variant", default="opticlock",
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help="variant: opticlock "
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"(default: %(default)s)")
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args = parser.parse_args()
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@ -14,15 +14,16 @@ from misoc.cores import gpio
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC, build_artiq_soc
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
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dds, spi, ad5360_monitor)
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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def __init__(self, platform, rtio_internal_clk, use_sma=True):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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@ -31,15 +32,17 @@ class _RTIOCRG(Module, AutoCSR):
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# 100 MHz when using 125MHz input
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self.clock_domains.cd_ext_clkout = ClockDomain(reset_less=True)
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ext_clkout = platform.request("user_sma_gpio_p_33")
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self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)
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if use_sma:
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ext_clkout = platform.request("user_sma_gpio_p_33")
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self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)
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rtio_external_clk = Signal()
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 8.0)
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self.specials += Instance("IBUFDS",
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=rtio_external_clk)
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if use_sma:
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 8.0)
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self.specials += Instance("IBUFDS",
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=rtio_external_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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@ -201,7 +204,7 @@ _urukul = [
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]
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class _NIST_Ions(MiniSoC, AMPSoC):
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class _Standalone_Base(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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@ -273,12 +276,12 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.csr_devices.append("rtio_analyzer")
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class NIST_CLOCK(_NIST_Ions):
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class NIST_CLOCK(_Standalone_Base):
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"""
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NIST clock hardware, with old backplane and 11 DDS channels
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"""
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def __init__(self, **kwargs):
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_NIST_Ions.__init__(self, **kwargs)
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_Standalone_Base.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(nist_clock.fmc_adapter_io)
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@ -374,13 +377,13 @@ class NIST_CLOCK(_NIST_Ions):
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self.add_rtio(rtio_channels)
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class NIST_QC2(_NIST_Ions):
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class NIST_QC2(_Standalone_Base):
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"""
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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and 24 DDS channels. Two backplanes are used.
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"""
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def __init__(self, **kwargs):
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_NIST_Ions.__init__(self, **kwargs)
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_Standalone_Base.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(nist_qc2.fmc_adapter_io)
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@ -444,25 +447,101 @@ class NIST_QC2(_NIST_Ions):
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self.add_rtio(rtio_channels)
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_sma_spi = [
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("sma_spi", 0,
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Subsignal("clk", Pins("Y23")), # user_sma_gpio_p
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Subsignal("cs_n", Pins("Y24")), # user_sma_gpio_n
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Subsignal("mosi", Pins("L25")), # user_sma_clk_p
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Subsignal("miso", Pins("K25")), # user_sma_clk_n
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IOStandard("LVCMOS25")),
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]
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class SMA_SPI(_Standalone_Base):
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"""
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SPI on 4 SMA for PDQ2 test/demo.
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"""
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def __init__(self, **kwargs):
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_Standalone_Base.__init__(self, **kwargs)
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platform = self.platform
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self.platform.add_extension(_sma_spi)
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rtio_channels = []
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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ams101_dac = self.platform.request("ams101_dac", 0)
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phy = ttl_simple.Output(ams101_dac.ldac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = spi.SPIMaster(ams101_dac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=4))
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phy = spi.SPIMaster(self.platform.request("sma_spi"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=128))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk,
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use_sma=False)
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self.csr_devices.append("rtio_crg")
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.rtio_crg.cd_rtio.clk.attr.add("keep")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder / single-FPGA KC705-based "
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"systems with AD9 DDS (NIST Ions hardware)")
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description="KC705 gateware and firmware builder")
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builder_args(parser)
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soc_kc705_args(parser)
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parser.add_argument("-H", "--hw-adapter", default="nist_clock",
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help="hardware adapter type: "
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"nist_clock/nist_qc2 "
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parser.add_argument("-V", "--variant", default="nist_clock",
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help="variant: "
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"nist_clock/nist_qc2/sma_spi "
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"(default: %(default)s)")
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args = parser.parse_args()
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hw_adapter = args.hw_adapter.lower()
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if hw_adapter == "nist_clock":
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variant = args.variant.lower()
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if variant == "nist_clock":
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cls = NIST_CLOCK
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elif hw_adapter == "nist_qc2":
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elif variant == "nist_qc2":
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cls = NIST_QC2
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elif variant == "sma_spi":
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cls = SMA_SPI
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else:
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raise SystemExit("Invalid hardware adapter string (-H/--hw-adapter)")
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raise SystemExit("Invalid variant (-V/--variant)")
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soc = cls(**soc_kc705_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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@ -1,157 +0,0 @@
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#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.build.generic_platform import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from misoc.targets.kc705 import soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.interconnect.csr import *
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from artiq.gateware.amp import build_artiq_soc
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, spi
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from .kc705_dds import _NIST_Ions
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# 10 MHz when using 125MHz input
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self.clock_domains.cd_ext_clkout = ClockDomain(reset_less=True)
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rtio_external_clk = Signal()
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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ext_clkout_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=50, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=ext_clkout_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
|
||||
Instance("BUFG", i_I=ext_clkout_clk, o_O=self.cd_ext_clkout.clk),
|
||||
|
||||
AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
|
||||
MultiReg(pll_locked, self._pll_locked.status)
|
||||
]
|
||||
|
||||
|
||||
_sma_spi = [
|
||||
("sma_spi", 0,
|
||||
Subsignal("clk", Pins("Y23")), # user_sma_gpio_p
|
||||
Subsignal("cs_n", Pins("Y24")), # user_sma_gpio_n
|
||||
Subsignal("mosi", Pins("L25")), # user_sma_clk_p
|
||||
Subsignal("miso", Pins("K25")), # user_sma_clk_n
|
||||
IOStandard("LVCMOS25")),
|
||||
]
|
||||
|
||||
|
||||
class SMA_SPI(_NIST_Ions):
|
||||
"""
|
||||
SPI on 4 SMA for PDQ2 test/demo.
|
||||
"""
|
||||
def __init__(self, **kwargs):
|
||||
_NIST_Ions.__init__(self, **kwargs)
|
||||
|
||||
platform = self.platform
|
||||
self.platform.add_extension(_sma_spi)
|
||||
|
||||
rtio_channels = []
|
||||
|
||||
phy = ttl_simple.Output(platform.request("user_led", 2))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
ams101_dac = self.platform.request("ams101_dac", 0)
|
||||
phy = ttl_simple.Output(ams101_dac.ldac)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
phy = spi.SPIMaster(ams101_dac)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(
|
||||
phy, ififo_depth=4))
|
||||
|
||||
phy = spi.SPIMaster(self.platform.request("sma_spi"))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(
|
||||
phy, ififo_depth=128))
|
||||
|
||||
self.config["HAS_RTIO_LOG"] = None
|
||||
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
||||
rtio_channels.append(rtio.LogChannel())
|
||||
|
||||
self.add_rtio(rtio_channels)
|
||||
|
||||
def add_rtio(self, rtio_channels):
|
||||
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
|
||||
self.csr_devices.append("rtio_crg")
|
||||
self.submodules.rtio_core = rtio.Core(rtio_channels)
|
||||
self.csr_devices.append("rtio_core")
|
||||
self.submodules.rtio = rtio.KernelInitiator()
|
||||
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
|
||||
rtio.DMA(self.get_native_sdram_if()))
|
||||
self.register_kernel_cpu_csrdevice("rtio")
|
||||
self.register_kernel_cpu_csrdevice("rtio_dma")
|
||||
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
||||
[self.rtio.cri, self.rtio_dma.cri],
|
||||
[self.rtio_core.cri])
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.rtio_crg.cd_rtio.clk.attr.add("keep")
|
||||
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
|
||||
self.platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
self.rtio_crg.cd_rtio.clk)
|
||||
|
||||
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
|
||||
self.get_native_sdram_if())
|
||||
self.csr_devices.append("rtio_analyzer")
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="ARTIQ device binary builder / "
|
||||
"KC705 SMA SPI demo/test for PDQ2")
|
||||
builder_args(parser)
|
||||
soc_kc705_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = SMA_SPI(**soc_kc705_argdict(args))
|
||||
build_artiq_soc(soc, builder_argdict(args))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
@ -3,6 +3,7 @@
|
||||
import argparse
|
||||
import os
|
||||
from collections import namedtuple
|
||||
import warnings
|
||||
|
||||
from migen import *
|
||||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
@ -23,11 +24,14 @@ from jesd204b.phy import JESD204BPhyTX
|
||||
from jesd204b.core import JESD204BCoreTX
|
||||
from jesd204b.core import JESD204BCoreTXControl
|
||||
|
||||
from artiq.gateware.amp import AMPSoC, build_artiq_soc
|
||||
from artiq.gateware.amp import AMPSoC
|
||||
from artiq.gateware import serwb
|
||||
from artiq.gateware import remote_csr
|
||||
from artiq.gateware import rtio
|
||||
from artiq.gateware.rtio.phy import ttl_simple, sawg
|
||||
from artiq.gateware.drtio.transceiver import gth_ultrascale
|
||||
from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
|
||||
from artiq.build_soc import build_artiq_soc
|
||||
from artiq import __version__ as artiq_version
|
||||
|
||||
|
||||
@ -129,7 +133,7 @@ class Standalone(MiniSoC, AMPSoC):
|
||||
}
|
||||
mem_map.update(MiniSoC.mem_map)
|
||||
|
||||
def __init__(self, with_sawg=False, **kwargs):
|
||||
def __init__(self, with_sawg, **kwargs):
|
||||
MiniSoC.__init__(self,
|
||||
cpu_type="or1k",
|
||||
sdram_controller_type="minicon",
|
||||
@ -248,33 +252,223 @@ class Standalone(MiniSoC, AMPSoC):
|
||||
self.csr_devices.append("rtio_analyzer")
|
||||
|
||||
|
||||
class Master(MiniSoC, AMPSoC):
|
||||
mem_map = {
|
||||
"cri_con": 0x10000000,
|
||||
"rtio": 0x20000000,
|
||||
"rtio_dma": 0x30000000,
|
||||
"drtio_aux": 0x50000000,
|
||||
"mailbox": 0x70000000
|
||||
}
|
||||
mem_map.update(MiniSoC.mem_map)
|
||||
|
||||
def __init__(self, **kwargs):
|
||||
MiniSoC.__init__(self,
|
||||
cpu_type="or1k",
|
||||
sdram_controller_type="minicon",
|
||||
l2_size=128*1024,
|
||||
ident=artiq_version,
|
||||
ethmac_nrxslots=4,
|
||||
ethmac_ntxslots=4,
|
||||
**kwargs)
|
||||
AMPSoC.__init__(self)
|
||||
|
||||
platform = self.platform
|
||||
rtio_clk_freq = 150e6
|
||||
|
||||
self.submodules += Microscope(platform.request("serial", 1),
|
||||
self.clk_freq)
|
||||
|
||||
# Si5324 used as a free-running oscillator, to avoid dependency on RTM.
|
||||
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
|
||||
self.csr_devices.append("si5324_rst_n")
|
||||
i2c = self.platform.request("i2c")
|
||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
self.csr_devices.append("i2c")
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
self.config["HAS_SI5324"] = None
|
||||
self.config["SI5324_FREE_RUNNING"] = None
|
||||
|
||||
self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
|
||||
self.submodules.transceiver = gth_ultrascale.GTH(
|
||||
clock_pads=platform.request("si5324_clkout"),
|
||||
data_pads=[platform.request("sfp", 0)],
|
||||
sys_clk_freq=self.clk_freq,
|
||||
rtio_clk_freq=rtio_clk_freq)
|
||||
|
||||
self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
|
||||
DRTIOMaster(self.transceiver.channels[0]))
|
||||
self.csr_devices.append("drtio0")
|
||||
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
|
||||
self.drtio0.aux_controller.bus)
|
||||
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
|
||||
self.config["HAS_DRTIO"] = None
|
||||
self.add_csr_group("drtio", ["drtio0"])
|
||||
self.add_memory_group("drtio_aux", ["drtio0_aux"])
|
||||
|
||||
rtio_clk_period = 1e9/rtio_clk_freq
|
||||
for gth in self.transceiver.gths:
|
||||
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
|
||||
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
gth.txoutclk, gth.rxoutclk)
|
||||
|
||||
rtio_channels = []
|
||||
for i in range(4):
|
||||
phy = ttl_simple.Output(platform.request("user_led", i))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
sma_io = platform.request("sma_io", 0)
|
||||
self.comb += sma_io.direction.eq(1)
|
||||
phy = ttl_simple.Output(sma_io.level)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
sma_io = platform.request("sma_io", 1)
|
||||
self.comb += sma_io.direction.eq(0)
|
||||
phy = ttl_simple.InOut(sma_io.level)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.submodules.rtio_core = rtio.Core(rtio_channels, glbl_fine_ts_width=3)
|
||||
self.csr_devices.append("rtio_core")
|
||||
|
||||
self.submodules.rtio = rtio.KernelInitiator()
|
||||
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
|
||||
rtio.DMA(self.get_native_sdram_if()))
|
||||
self.register_kernel_cpu_csrdevice("rtio")
|
||||
self.register_kernel_cpu_csrdevice("rtio_dma")
|
||||
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
||||
[self.rtio.cri, self.rtio_dma.cri],
|
||||
[self.rtio_core.cri, self.drtio0.cri])
|
||||
self.register_kernel_cpu_csrdevice("cri_con")
|
||||
|
||||
|
||||
class Satellite(BaseSoC):
|
||||
mem_map = {
|
||||
"drtio_aux": 0x50000000,
|
||||
}
|
||||
mem_map.update(BaseSoC.mem_map)
|
||||
|
||||
def __init__(self, with_sawg, **kwargs):
|
||||
BaseSoC.__init__(self,
|
||||
cpu_type="or1k",
|
||||
sdram_controller_type="minicon",
|
||||
l2_size=128*1024,
|
||||
ident=artiq_version,
|
||||
**kwargs)
|
||||
|
||||
if with_sawg:
|
||||
warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.")
|
||||
|
||||
platform = self.platform
|
||||
rtio_clk_freq = 150e6
|
||||
|
||||
self.submodules += Microscope(platform.request("serial", 1),
|
||||
self.clk_freq)
|
||||
|
||||
rtio_channels = []
|
||||
for i in range(4):
|
||||
phy = ttl_simple.Output(platform.request("user_led", i))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
sma_io = platform.request("sma_io", 0)
|
||||
self.comb += sma_io.direction.eq(1)
|
||||
phy = ttl_simple.Output(sma_io.level)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
sma_io = platform.request("sma_io", 1)
|
||||
self.comb += sma_io.direction.eq(0)
|
||||
phy = ttl_simple.InOut(sma_io.level)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
|
||||
self.submodules.transceiver = gth_ultrascale.GTH(
|
||||
clock_pads=platform.request("si5324_clkout"),
|
||||
data_pads=[platform.request("sfp", 0)],
|
||||
sys_clk_freq=self.clk_freq,
|
||||
rtio_clk_freq=rtio_clk_freq)
|
||||
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
|
||||
self.submodules.drtio0 = rx0(DRTIOSatellite(
|
||||
self.transceiver.channels[0], rtio_channels))
|
||||
self.csr_devices.append("drtio0")
|
||||
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
|
||||
self.drtio0.aux_controller.bus)
|
||||
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
|
||||
self.config["HAS_DRTIO"] = None
|
||||
self.add_csr_group("drtio", ["drtio0"])
|
||||
self.add_memory_group("drtio_aux", ["drtio0_aux"])
|
||||
|
||||
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
|
||||
si5324_clkin = platform.request("si5324_clkin")
|
||||
self.specials += \
|
||||
Instance("OBUFDS",
|
||||
i_I=ClockSignal("rtio_rx0"),
|
||||
o_O=si5324_clkin.p, o_OB=si5324_clkin.n
|
||||
)
|
||||
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
|
||||
self.csr_devices.append("si5324_rst_n")
|
||||
i2c = self.platform.request("i2c")
|
||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
self.csr_devices.append("i2c")
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
self.config["HAS_SI5324"] = None
|
||||
|
||||
rtio_clk_period = 1e9/rtio_clk_freq
|
||||
gth = self.transceiver.gths[0]
|
||||
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
|
||||
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
gth.txoutclk, gth.rxoutclk)
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="ARTIQ device binary builder / Sayma AMC stand-alone")
|
||||
description="Sayma AMC gateware and firmware builder")
|
||||
builder_args(parser)
|
||||
soc_sdram_args(parser)
|
||||
parser.add_argument("-V", "--variant", default="standalone",
|
||||
help="variant: "
|
||||
"standalone/master/satellite "
|
||||
"(default: %(default)s)")
|
||||
parser.add_argument("--rtm-csr-csv",
|
||||
default=os.path.join("artiq_sayma_rtm", "sayma_rtm_csr.csv"),
|
||||
help="CSV file listing remote CSRs on RTM (default: %(default)s)")
|
||||
parser.add_argument("--with-sawg",
|
||||
parser.add_argument("--without-sawg",
|
||||
default=False, action="store_true",
|
||||
help="Add SAWG RTIO channels feeding the JESD links. If not "
|
||||
"specified, fixed sawtooth generators are used. "
|
||||
"(default: %(default)s)")
|
||||
help="Remove SAWG RTIO channels feeding the JESD links (speeds up "
|
||||
"compilation time). Replaces them with fixed sawtooth generators.")
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = Standalone(with_sawg=args.with_sawg, **soc_sdram_argdict(args))
|
||||
variant = args.variant.lower()
|
||||
if variant == "standalone":
|
||||
cls = Standalone
|
||||
elif variant == "master":
|
||||
cls = Master
|
||||
elif variant == "satellite":
|
||||
cls = Satellite
|
||||
soc = cls(with_sawg=not args.without_sawg, **soc_sdram_argdict(args))
|
||||
|
||||
remote_csr_regions = remote_csr.get_remote_csr_regions(
|
||||
soc.mem_map["serwb"] | soc.shadow_base,
|
||||
args.rtm_csr_csv)
|
||||
for name, origin, busword, csrs in remote_csr_regions:
|
||||
soc.add_csr_region(name, origin, busword, csrs)
|
||||
# Configuration for RTM peripherals. Keep in sync with sayma_rtm.py!
|
||||
soc.config["HAS_HMC830_7043"] = None
|
||||
soc.config["CONVERTER_SPI_HMC830_CS"] = 0
|
||||
soc.config["CONVERTER_SPI_HMC7043_CS"] = 1
|
||||
soc.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2
|
||||
# DRTIO variants do not use the RTM yet.
|
||||
if variant not in {"master", "satellite"}:
|
||||
remote_csr_regions = remote_csr.get_remote_csr_regions(
|
||||
soc.mem_map["serwb"] | soc.shadow_base,
|
||||
args.rtm_csr_csv)
|
||||
for name, origin, busword, csrs in remote_csr_regions:
|
||||
soc.add_csr_region(name, origin, busword, csrs)
|
||||
# Configuration for RTM peripherals. Keep in sync with sayma_rtm.py!
|
||||
soc.config["HAS_HMC830_7043"] = None
|
||||
soc.config["CONVERTER_SPI_HMC830_CS"] = 0
|
||||
soc.config["CONVERTER_SPI_HMC7043_CS"] = 1
|
||||
soc.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2
|
||||
|
||||
build_artiq_soc(soc, builder_argdict(args))
|
||||
|
||||
@ -1,131 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import argparse
|
||||
|
||||
from migen import *
|
||||
from migen.build.generic_platform import *
|
||||
|
||||
from misoc.cores import spi as spi_csr
|
||||
from misoc.cores import gpio
|
||||
from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
|
||||
from misoc.integration.builder import builder_args, builder_argdict
|
||||
from misoc.targets.sayma_amc import MiniSoC
|
||||
|
||||
from microscope import *
|
||||
|
||||
from artiq.gateware.amp import AMPSoC, build_artiq_soc
|
||||
from artiq.gateware import rtio
|
||||
from artiq.gateware.rtio.phy import ttl_simple
|
||||
from artiq.gateware.drtio.transceiver import gth_ultrascale
|
||||
from artiq.gateware.drtio import DRTIOMaster
|
||||
from artiq import __version__ as artiq_version
|
||||
|
||||
|
||||
class Master(MiniSoC, AMPSoC):
|
||||
mem_map = {
|
||||
"cri_con": 0x10000000,
|
||||
"rtio": 0x20000000,
|
||||
"rtio_dma": 0x30000000,
|
||||
"drtio_aux": 0x50000000,
|
||||
"mailbox": 0x70000000
|
||||
}
|
||||
mem_map.update(MiniSoC.mem_map)
|
||||
|
||||
def __init__(self, **kwargs):
|
||||
MiniSoC.__init__(self,
|
||||
cpu_type="or1k",
|
||||
sdram_controller_type="minicon",
|
||||
l2_size=128*1024,
|
||||
ident=artiq_version,
|
||||
ethmac_nrxslots=4,
|
||||
ethmac_ntxslots=4,
|
||||
**kwargs)
|
||||
AMPSoC.__init__(self)
|
||||
|
||||
platform = self.platform
|
||||
rtio_clk_freq = 150e6
|
||||
|
||||
self.submodules += Microscope(platform.request("serial", 1),
|
||||
self.clk_freq)
|
||||
|
||||
# Si5324 used as a free-running oscillator, to avoid dependency on RTM.
|
||||
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
|
||||
self.csr_devices.append("si5324_rst_n")
|
||||
i2c = self.platform.request("i2c")
|
||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
self.csr_devices.append("i2c")
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
self.config["HAS_SI5324"] = None
|
||||
self.config["SI5324_FREE_RUNNING"] = None
|
||||
|
||||
self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
|
||||
self.submodules.transceiver = gth_ultrascale.GTH(
|
||||
clock_pads=platform.request("si5324_clkout"),
|
||||
data_pads=[platform.request("sfp", 0)],
|
||||
sys_clk_freq=self.clk_freq,
|
||||
rtio_clk_freq=rtio_clk_freq)
|
||||
|
||||
self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
|
||||
DRTIOMaster(self.transceiver.channels[0]))
|
||||
self.csr_devices.append("drtio0")
|
||||
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
|
||||
self.drtio0.aux_controller.bus)
|
||||
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
|
||||
self.config["HAS_DRTIO"] = None
|
||||
self.add_csr_group("drtio", ["drtio0"])
|
||||
self.add_memory_group("drtio_aux", ["drtio0_aux"])
|
||||
|
||||
rtio_clk_period = 1e9/rtio_clk_freq
|
||||
for gth in self.transceiver.gths:
|
||||
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
|
||||
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
gth.txoutclk, gth.rxoutclk)
|
||||
|
||||
rtio_channels = []
|
||||
for i in range(4):
|
||||
phy = ttl_simple.Output(platform.request("user_led", i))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
sma_io = platform.request("sma_io", 0)
|
||||
self.comb += sma_io.direction.eq(1)
|
||||
phy = ttl_simple.Output(sma_io.level)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
sma_io = platform.request("sma_io", 1)
|
||||
self.comb += sma_io.direction.eq(0)
|
||||
phy = ttl_simple.InOut(sma_io.level)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.submodules.rtio_core = rtio.Core(rtio_channels, glbl_fine_ts_width=3)
|
||||
self.csr_devices.append("rtio_core")
|
||||
|
||||
self.submodules.rtio = rtio.KernelInitiator()
|
||||
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
|
||||
rtio.DMA(self.get_native_sdram_if()))
|
||||
self.register_kernel_cpu_csrdevice("rtio")
|
||||
self.register_kernel_cpu_csrdevice("rtio_dma")
|
||||
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
||||
[self.rtio.cri, self.rtio_dma.cri],
|
||||
[self.rtio_core.cri, self.drtio0.cri])
|
||||
self.register_kernel_cpu_csrdevice("cri_con")
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="ARTIQ device binary builder / Sayma DRTIO master")
|
||||
builder_args(parser)
|
||||
soc_sdram_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = Master(**soc_sdram_argdict(args))
|
||||
build_artiq_soc(soc, builder_argdict(args))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
@ -1,121 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import argparse
|
||||
import os
|
||||
|
||||
from migen import *
|
||||
from migen.build.generic_platform import *
|
||||
from misoc.cores import spi as spi_csr
|
||||
from misoc.cores import gpio
|
||||
from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
|
||||
from misoc.integration.builder import *
|
||||
from misoc.targets.sayma_amc import BaseSoC
|
||||
|
||||
from microscope import *
|
||||
|
||||
from artiq.gateware import rtio
|
||||
from artiq.gateware.rtio.phy import ttl_simple
|
||||
from artiq.gateware.drtio.transceiver import gth_ultrascale
|
||||
from artiq.gateware.drtio import DRTIOSatellite
|
||||
from artiq import __version__ as artiq_version
|
||||
from artiq import __artiq_dir__ as artiq_dir
|
||||
|
||||
|
||||
class Satellite(BaseSoC):
|
||||
mem_map = {
|
||||
"drtio_aux": 0x50000000,
|
||||
}
|
||||
mem_map.update(BaseSoC.mem_map)
|
||||
|
||||
def __init__(self, **kwargs):
|
||||
BaseSoC.__init__(self,
|
||||
cpu_type="or1k",
|
||||
sdram_controller_type="minicon",
|
||||
l2_size=128*1024,
|
||||
ident=artiq_version,
|
||||
**kwargs)
|
||||
|
||||
platform = self.platform
|
||||
rtio_clk_freq = 150e6
|
||||
|
||||
self.submodules += Microscope(platform.request("serial", 1),
|
||||
self.clk_freq)
|
||||
|
||||
rtio_channels = []
|
||||
for i in range(4):
|
||||
phy = ttl_simple.Output(platform.request("user_led", i))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
sma_io = platform.request("sma_io", 0)
|
||||
self.comb += sma_io.direction.eq(1)
|
||||
phy = ttl_simple.Output(sma_io.level)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
sma_io = platform.request("sma_io", 1)
|
||||
self.comb += sma_io.direction.eq(0)
|
||||
phy = ttl_simple.InOut(sma_io.level)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
|
||||
self.submodules.transceiver = gth_ultrascale.GTH(
|
||||
clock_pads=platform.request("si5324_clkout"),
|
||||
data_pads=[platform.request("sfp", 0)],
|
||||
sys_clk_freq=self.clk_freq,
|
||||
rtio_clk_freq=rtio_clk_freq)
|
||||
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
|
||||
self.submodules.drtio0 = rx0(DRTIOSatellite(
|
||||
self.transceiver.channels[0], rtio_channels))
|
||||
self.csr_devices.append("drtio0")
|
||||
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
|
||||
self.drtio0.aux_controller.bus)
|
||||
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
|
||||
self.config["HAS_DRTIO"] = None
|
||||
self.add_csr_group("drtio", ["drtio0"])
|
||||
self.add_memory_group("drtio_aux", ["drtio0_aux"])
|
||||
|
||||
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
|
||||
si5324_clkin = platform.request("si5324_clkin")
|
||||
self.specials += \
|
||||
Instance("OBUFDS",
|
||||
i_I=ClockSignal("rtio_rx0"),
|
||||
o_O=si5324_clkin.p, o_OB=si5324_clkin.n
|
||||
)
|
||||
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
|
||||
self.csr_devices.append("si5324_rst_n")
|
||||
i2c = self.platform.request("i2c")
|
||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
self.csr_devices.append("i2c")
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
self.config["HAS_SI5324"] = None
|
||||
|
||||
rtio_clk_period = 1e9/rtio_clk_freq
|
||||
gth = self.transceiver.gths[0]
|
||||
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
|
||||
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
gth.txoutclk, gth.rxoutclk)
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="ARTIQ device binary builder / Sayma DRTIO satellite")
|
||||
builder_args(parser)
|
||||
soc_sdram_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = Satellite(**soc_sdram_argdict(args))
|
||||
firmware_dir = os.path.join(artiq_dir, "firmware")
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.software_packages = []
|
||||
builder.add_software_package("bootloader", os.path.join(firmware_dir, "bootloader"))
|
||||
builder.add_software_package("satman", os.path.join(firmware_dir, "satman"))
|
||||
builder.build()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
@ -3,7 +3,7 @@
|
||||
SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kasli-opticlock
|
||||
mkdir -p $SOC_PREFIX
|
||||
|
||||
V=1 $PYTHON -m artiq.gateware.targets.kasli --variant opticlock
|
||||
V=1 $PYTHON -m artiq.gateware.targets.kasli -V opticlock
|
||||
cp misoc_opticlock_kasli/gateware/top.bit $SOC_PREFIX
|
||||
cp misoc_opticlock_kasli/software/bootloader/bootloader.bin $SOC_PREFIX
|
||||
cp misoc_opticlock_kasli/software/runtime/runtime.{elf,fbi} $SOC_PREFIX
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-nist_clock
|
||||
mkdir -p $SOC_PREFIX
|
||||
|
||||
V=1 $PYTHON -m artiq.gateware.targets.kc705_dds -H nist_clock
|
||||
V=1 $PYTHON -m artiq.gateware.targets.kc705 -V nist_clock
|
||||
cp misoc_nist_clock_kc705/gateware/top.bit $SOC_PREFIX
|
||||
cp misoc_nist_clock_kc705/software/bootloader/bootloader.bin $SOC_PREFIX
|
||||
cp misoc_nist_clock_kc705/software/runtime/runtime.{elf,fbi} $SOC_PREFIX
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-nist_qc2
|
||||
mkdir -p $SOC_PREFIX
|
||||
|
||||
V=1 $PYTHON -m artiq.gateware.targets.kc705_dds -H nist_qc2
|
||||
V=1 $PYTHON -m artiq.gateware.targets.kc705 -V nist_qc2
|
||||
cp misoc_nist_qc2_kc705/gateware/top.bit $SOC_PREFIX
|
||||
cp misoc_nist_qc2_kc705/software/bootloader/bootloader.bin $SOC_PREFIX
|
||||
cp misoc_nist_qc2_kc705/software/runtime/runtime.{elf,fbi} $SOC_PREFIX
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/sayma_amc-standalone
|
||||
mkdir -p $SOC_PREFIX
|
||||
|
||||
V=1 $PYTHON -m artiq.gateware.targets.sayma_amc_standalone --rtm-csr-csv $SP_DIR/artiq/binaries/sayma_rtm/sayma_rtm_csr.csv
|
||||
V=1 $PYTHON -m artiq.gateware.targets.sayma_amc -V standalone --rtm-csr-csv $SP_DIR/artiq/binaries/sayma_rtm/sayma_rtm_csr.csv
|
||||
cp misoc_standalone_sayma_amc/gateware/top.bit $SOC_PREFIX
|
||||
cp misoc_standalone_sayma_amc/software/bootloader/bootloader.bin $SOC_PREFIX
|
||||
cp misoc_standalone_sayma_amc/software/runtime/runtime.{elf,fbi} $SOC_PREFIX
|
||||
|
||||
@ -217,7 +217,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
|
||||
|
||||
* For KC705::
|
||||
|
||||
$ python3 -m artiq.gateware.targets.kc705_dds -H nist_clock # or nist_qc2
|
||||
$ python3 -m artiq.gateware.targets.kc705 -V nist_clock # or nist_qc2
|
||||
|
||||
.. note:: Add ``--toolchain ise`` if you wish to use ISE instead of Vivado. ISE needs a separate installation step.
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user