gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200

2017-12-21 23:52:44 +01:00 · 2017-12-21 23:52:44 +01:00 · 86825a852c
parent 8adb50037f
commit 86825a852c
1 changed files with 4 additions and 0 deletions
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@ -77,6 +77,10 @@ class SaymaRTM(Module):
        self.crg.cd_sys.clk.attr.add("keep")
        clk_freq = 125e6
        platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
+        platform.add_period_constraint(self.crg.cd_clk200.clk, 5.0)
+        platform.add_false_path_constraints(
+            self.crg.cd_sys.clk,
+            self.crg.cd_clk200.clk)

        self.submodules.rtm_identifier = RTMIdentifier()
        csr_devices.append("rtm_identifier")