sayma_rtm: constrain serwb clock input

2018-01-23 13:54:53 +00:00 · 2018-01-23 13:54:53 +00:00 · b5c035bb52
parent aada38f508
commit b5c035bb52
1 changed files with 1 additions and 0 deletions
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@ -148,6 +148,7 @@ class SaymaRTM(Module):
        self.submodules += serwb_pll

        serwb_pads = platform.request("amc_rtm_serwb")
+        platform.add_period_constraint(serwb_pads.clk_p, 16.)
        serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="slave")
        self.submodules.serwb_phy_rtm = serwb_phy_rtm
        self.comb += self.crg.reset.eq(serwb_phy_rtm.init.reset)