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sayma_amc: remove RTM bitstream upload core. Closes #908
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@ -160,9 +160,10 @@ class Standalone(MiniSoC, AMPSoC):
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# RTM bitstream upload
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rtm_fpga_cfg = platform.request("rtm_fpga_cfg")
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self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg)
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self.csr_devices.append("rtm_fpga_cfg")
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# https://github.com/m-labs/artiq/issues/908#issuecomment-363650534
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#rtm_fpga_cfg = platform.request("rtm_fpga_cfg")
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#self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg)
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#self.csr_devices.append("rtm_fpga_cfg")
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# AMC/RTM serwb
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serwb_pll = serwb.phy.SERWBPLL(125e6, 625e6, vco_div=2)
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