sayma: fix AD9154NoSAWG ramp clock domain

2018-01-10 12:11:33 +08:00 · 2018-01-10 12:11:33 +08:00 · 04b2fd3e13
parent 0ce63e7f4a
commit 04b2fd3e13
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/targets/sayma_amc_standalone.py
+++ b/artiq/gateware/targets/sayma_amc_standalone.py
@ -107,7 +107,7 @@ class AD9154NoSAWG(Module, AutoCSR):

        for i, conv in enumerate(self.jesd.core.sink.flatten()):
            ramp = Signal(16)
-            self.sync += ramp.eq(ramp + (1 << 9 + i))
+            self.sync.rtio += ramp.eq(ramp + (1 << 9 + i))
            self.comb += conv.eq(Cat(ramp
                for i in range(len(conv) // len(ramp))))