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artiq
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f8c2d54e75
artiq
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artiq
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gateware
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Sebastien Bourdeauducq
f8c2d54e75
ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma
2018-03-21 13:01:38 +08:00
..
__init__.py
package everything to rebuild core device binaries
2015-11-09 10:47:14 +08:00
kasli.py
Fix typos.
2018-03-19 09:42:18 +00:00
kc705.py
kc705: switch backplane spi to spi2
2018-03-01 11:19:18 +01:00
sayma_amc.py
ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma
2018-03-21 13:01:38 +08:00
sayma_rtm.py
sayma_rtm: fix serwb timing constraints (was causing the gated clock warning)
2018-03-12 11:25:29 +01:00