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kc705_dds: add urukul spi/ttl channels
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@ -34,7 +34,7 @@ device_db = {
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"class": "DDSGroupAD9914",
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"arguments": {
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"sysclk": 3e9,
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"first_dds_bus_channel": 32,
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"first_dds_bus_channel": 39,
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"dds_bus_count": 2,
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"dds_channel_count": 3
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}
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@ -191,25 +191,68 @@ device_db = {
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"arguments": {"spi_device": "spi_zotino", "ldac_device": "ttl_zotino_ldac"}
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},
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"spi_urukul": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"class": "SPIMaster",
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"arguments": {"channel": 32}
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},
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"ttl_urukul_io_update": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 33}
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},
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"ttl_urukul_dds_reset": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 34}
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},
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"ttl_urukul_sw0": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 35}
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},
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"ttl_urukul_sw1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 36}
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},
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"ttl_urukul_sw2": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 37}
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},
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"ttl_urukul_sw3": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 38}
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},
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# AD9914 DDS
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"dds0": {
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 32, "channel": 0},
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"arguments": {"bus_channel": 39, "channel": 0},
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"comment": "Comments work in DDS panel as well"
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},
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"dds1": {
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 32, "channel": 1}
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"arguments": {"bus_channel": 39, "channel": 1}
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},
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"dds2": {
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 32, "channel": 2}
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"arguments": {"bus_channel": 39, "channel": 2}
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},
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# Controllers
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@ -353,6 +353,17 @@ class NIST_CLOCK(_NIST_Ions):
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self.submodules += dac_monitor
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sdac_phy.probes.extend(dac_monitor.probes)
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phy = spi.SPIMaster(self.platform.request("urukul_spi_p"),
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self.platform.request("urukul_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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for signal in "io_update dds_reset sw0 sw1 sw2 sw3".split():
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pads = platform.request("urukul_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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@ -76,28 +76,42 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
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+--------------------+-----------------------+--------------+
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| 31 | ZOTINO_LDAC | Output |
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+--------------------+-----------------------+--------------+
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| 33 | URUKUL_IO_UPDATE | Output |
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+--------------------+-----------------------+--------------+
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| 34 | URUKUL_DDS_RESET | Output |
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+--------------------+-----------------------+--------------+
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| 35 | URUKUL_SW0 | Output |
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+--------------------+-----------------------+--------------+
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| 36 | URUKUL_SW1 | Output |
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+--------------------+-----------------------+--------------+
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| 37 | URUKUL_SW2 | Output |
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+--------------------+-----------------------+--------------+
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| 38 | URUKUL_SW3 | Output |
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+--------------------+-----------------------+--------------+
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The board has RTIO SPI buses mapped as follows:
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+--------------+--------------+--------------+--------------+------------+
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| RTIO channel | CS_N | MOSI | MISO | CLK |
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+==============+==============+==============+==============+============+
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| 22 | AMS101_CS_N | AMS101_MOSI | | AMS101_CLK |
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+--------------+--------------+--------------+--------------+------------+
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| 23 | SPI0_CS_N | SPI0_MOSI | SPI0_MISO | SPI0_CLK |
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+--------------+--------------+--------------+--------------+------------+
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| 24 | SPI1_CS_N | SPI1_MOSI | SPI1_MISO | SPI1_CLK |
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+--------------+--------------+--------------+--------------+------------+
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| 25 | SPI2_CS_N | SPI2_MOSI | SPI2_MISO | SPI2_CLK |
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+--------------+--------------+--------------+--------------+------------+
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| 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK|
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+--------------+--------------+--------------+--------------+------------+
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| 30 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK |
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+--------------+--------------+--------------+--------------+------------+
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+--------------+------------------+--------------+--------------+------------+
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| RTIO channel | CS_N | MOSI | MISO | CLK |
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+==============+==================+==============+==============+============+
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| 22 | AMS101_CS_N | AMS101_MOSI | | AMS101_CLK |
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+--------------+------------------+--------------+--------------+------------+
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| 23 | SPI0_CS_N | SPI0_MOSI | SPI0_MISO | SPI0_CLK |
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+--------------+------------------+--------------+--------------+------------+
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| 24 | SPI1_CS_N | SPI1_MOSI | SPI1_MISO | SPI1_CLK |
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+--------------+------------------+--------------+--------------+------------+
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| 25 | SPI2_CS_N | SPI2_MOSI | SPI2_MISO | SPI2_CLK |
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+--------------+------------------+--------------+--------------+------------+
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| 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK|
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+--------------+------------------+--------------+--------------+------------+
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| 30 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK |
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+--------------+------------------+--------------+--------------+------------+
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| 32 | URUKUL_CS_N[0:2] | URUKUL_MOSI | URUKUL_MISO | URUKUL_CLK |
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+--------------+------------------+--------------+--------------+------------+
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The DDS bus is on channel 32.
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The DDS bus is on channel 39.
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This configuration supports a Zotino connected to the KC705 FMC HPC through a FMC DIO 32ch LVDS v1.2 and a VHDCI breakout board rev 1.0. On the VHDCI breakout board, the VHDCI cable to the KC705 should be plugged into to the bottom connector, and the EEM cable to the Zotino should be connected to J41.
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This configuration supports a Zotino and/or an Urukul connected to the KC705 FMC HPC through a FMC DIO 32ch LVDS v1.2 and a VHDCI breakout board rev 1.0 or rev 1.1. On the VHDCI breakout board, the VHDCI cable to the KC705 should be plugged into to the bottom connector. The EEM cable to the Zotino should be connected to J41 and the EEM cables to Urukul to J42 and J43.
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The shift registers on the FMC card should be configured to set the directions of its LVDS buffers, using :mod:`artiq.coredevice.shiftreg`.
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