mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 03:08:27 +08:00
sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)
This commit is contained in:
parent
039dee4c8e
commit
73985a9215
@ -176,11 +176,7 @@ class Standalone(MiniSoC, AMPSoC):
|
||||
self.csr_devices.append("serwb_phy_amc")
|
||||
|
||||
serwb_phy_amc.serdes.cd_serwb_serdes.clk.attr.add("keep")
|
||||
serwb_phy_amc.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
|
||||
serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
|
||||
platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes.clk, 40*1e9/serwb_pll.linerate),
|
||||
platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_20x.clk, 2*1e9/serwb_pll.linerate),
|
||||
platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk, 8*1e9/serwb_pll.linerate)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
serwb_phy_amc.serdes.cd_serwb_serdes.clk,
|
||||
|
Loading…
Reference in New Issue
Block a user