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https://github.com/m-labs/artiq.git
synced 2024-12-25 11:18:27 +08:00
drtio: add Sayma top-level designs
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4fbc8772a5
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@ -77,6 +77,8 @@ fn startup() {
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#[cfg(has_i2c)]
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board::i2c::init();
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#[cfg(si5324_free_running)]
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setup_si5324_free_running();
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#[cfg(has_hmc830_7043)]
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board::hmc830_7043::init().expect("cannot initialize HMC830/7043");
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#[cfg(has_ad9154)]
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@ -91,6 +93,23 @@ fn startup() {
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}
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}
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#[cfg(si5324_free_running)]
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fn setup_si5324_free_running()
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{
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// 150MHz output (hardcoded)
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const SI5324_SETTINGS: board::si5324::FrequencySettings
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= board::si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 9370,
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n32 : 7139,
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bwsel : 3
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};
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board::si5324::setup(&SI5324_SETTINGS).expect("cannot initialize Si5324");
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}
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#[cfg(has_ethmac)]
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fn startup_ethernet() {
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let hardware_addr;
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122
artiq/gateware/targets/sayma_amc_drtio_master.py
Executable file
122
artiq/gateware/targets/sayma_amc_drtio_master.py
Executable file
@ -0,0 +1,122 @@
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#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.build.generic_platform import *
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from misoc.cores import spi as spi_csr
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from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.targets.sayma_amc import MiniSoC
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from artiq.gateware.amp import AMPSoC, build_artiq_soc
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio import DRTIOMaster
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from artiq import __version__ as artiq_version
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class Master(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"drtio_aux": 0x50000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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platform = self.platform
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# Si5324 used as a free-running oscillator, to avoid dependency on RTM.
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_FREE_RUNNING"] = None
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self.submodules.transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=[platform.request("sfp_tx")],
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rx_pads=[platform.request("sfp_rx")],
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sys_clk_freq=self.clk_freq)
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self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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DRTIOMaster(self.transceiver.channels[0]))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
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platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
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platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.transceiver.txoutclk, self.transceiver.rxoutclk)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri, self.drtio0.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder / Sayma DRTIO master")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = Master(**soc_sdram_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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if __name__ == "__main__":
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main()
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113
artiq/gateware/targets/sayma_amc_drtio_satellite.py
Executable file
113
artiq/gateware/targets/sayma_amc_drtio_satellite.py
Executable file
@ -0,0 +1,113 @@
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#!/usr/bin/env python3
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import argparse
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import os
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from migen import *
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from migen.build.generic_platform import *
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from misoc.cores import spi as spi_csr
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from misoc.cores import gpio
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from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.targets.sayma_amc import BaseSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio import DRTIOSatellite
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from artiq import __version__ as artiq_version
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from artiq import __artiq_dir__ as artiq_dir
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class Satellite(BaseSoC):
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mem_map = {
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"drtio_aux": 0x50000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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**kwargs)
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platform = self.platform
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.transceiver = gth_7series.GTH(
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=platform.request("sfp_tx"),
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rx_pads=platform.request("sfp_rx"),
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sys_clk_freq=self.clk_freq)
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer0 = rx0(gth_ultrascale.RXSynchronizer(
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self.transceiver.rtio_clk_freq, initial_phase=180.0))
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.transceiver.channels[0], rtio_channels, self.rx_synchronizer0))
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self.csr_devices.append("rx_synchronizer0")
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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self.config["RTIO_FREQUENCY"] = str(self.transceiver.rtio_clk_freq/1e6)
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si5324_clkin = platform.request("si5324_clkin")
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self.specials += \
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Instance("OBUFDS",
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i_I=ClockSignal("rtio_rx0"),
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o_O=si5324_clkin.p, o_OB=si5324_clkin.n
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)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
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platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
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platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.transceiver.txoutclk, self.transceiver.rxoutclk)
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder / Sayma DRTIO satellite")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = Satellite(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.add_software_package("satman", os.path.join(artiq_dir, "firmware", "satman"))
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builder.build()
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if __name__ == "__main__":
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main()
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