mirror of https://github.com/m-labs/artiq.git
drtio: remove KC705/GTX support
This commit is contained in:
parent
0681d472c7
commit
ebdbaaad32
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@ -1,265 +0,0 @@
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.cores.code_8b10b import Encoder, Decoder
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from misoc.interconnect.csr import *
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from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
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from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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class GTX_20X(Module, TransceiverInterface):
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# Only one channel is supported.
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#
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# The transceiver clock on clock_pads must be at the RTIO clock
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# frequency when clock_div2=False, and 2x that frequency when
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# clock_div2=True.
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def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
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clock_div2=False):
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encoder = ClockDomainsRenamer("rtio")(
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Encoder(2, True))
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self.submodules += encoder
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decoders = [ClockDomainsRenamer("rtio_rx0")(
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(Decoder(True))) for _ in range(2)]
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self.submodules += decoders
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TransceiverInterface.__init__(self, [ChannelInterface(encoder, decoders)])
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# transceiver direct clock outputs
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# useful to specify clock constraints in a way palatable to Vivado
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self.txoutclk = Signal()
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self.rxoutclk = Signal()
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# # #
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refclk = Signal()
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if clock_div2:
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_ODIV2=refclk
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)
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else:
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_O=refclk
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)
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cplllock = Signal()
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# TX generates RTIO clock, init must be in system domain
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tx_init = GTXInit(sys_clk_freq, False)
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# RX receives restart commands from RTIO domain
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rx_init = ClockDomainsRenamer("rtio")(
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GTXInit(self.rtio_clk_freq, True))
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self.submodules += tx_init, rx_init
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self.comb += tx_init.cplllock.eq(cplllock), \
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rx_init.cplllock.eq(cplllock)
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txdata = Signal(20)
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rxdata = Signal(20)
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self.specials += \
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Instance("GTXE2_CHANNEL",
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# PMA Attributes
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p_PMA_RSV=0x00018480,
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p_PMA_RSV2=0x2050,
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p_PMA_RSV3=0,
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p_PMA_RSV4=0,
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p_RX_BIAS_CFG=0b100,
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p_RX_CM_TRIM=0b010,
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p_RX_OS_CFG=0b10000000,
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p_RX_CLK25_DIV=5,
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p_TX_CLK25_DIV=5,
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# Power-Down Attributes
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p_PD_TRANS_TIME_FROM_P2=0x3c,
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p_PD_TRANS_TIME_NONE_P2=0x3c,
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p_PD_TRANS_TIME_TO_P2=0x64,
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# CPLL
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p_CPLL_CFG=0xBC07DC,
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p_CPLL_FBDIV=4,
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p_CPLL_FBDIV_45=5,
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p_CPLL_REFCLK_DIV=1,
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p_RXOUT_DIV=2,
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p_TXOUT_DIV=2,
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o_CPLLLOCK=cplllock,
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i_CPLLLOCKEN=1,
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i_CPLLREFCLKSEL=0b001,
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i_TSTIN=2**20-1,
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i_GTREFCLK0=refclk,
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# TX clock
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p_TXBUF_EN="FALSE",
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p_TX_XCLK_SEL="TXUSR",
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o_TXOUTCLK=self.txoutclk,
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i_TXSYSCLKSEL=0b00,
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i_TXOUTCLKSEL=0b11,
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# TX Startup/Reset
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i_GTTXRESET=tx_init.gtXxreset,
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o_TXRESETDONE=tx_init.Xxresetdone,
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i_TXDLYSRESET=tx_init.Xxdlysreset,
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o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone,
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o_TXPHALIGNDONE=tx_init.Xxphaligndone,
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i_TXUSERRDY=tx_init.Xxuserrdy,
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# TX data
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p_TX_DATA_WIDTH=20,
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p_TX_INT_DATAWIDTH=0,
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i_TXCHARDISPMODE=Cat(txdata[9], txdata[19]),
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i_TXCHARDISPVAL=Cat(txdata[8], txdata[18]),
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i_TXDATA=Cat(txdata[:8], txdata[10:18]),
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i_TXUSRCLK=ClockSignal("rtio"),
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i_TXUSRCLK2=ClockSignal("rtio"),
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# TX electrical
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i_TXBUFDIFFCTRL=0b100,
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i_TXDIFFCTRL=0b1000,
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# RX Startup/Reset
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i_GTRXRESET=rx_init.gtXxreset,
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o_RXRESETDONE=rx_init.Xxresetdone,
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i_RXDLYSRESET=rx_init.Xxdlysreset,
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o_RXDLYSRESETDONE=rx_init.Xxdlysresetdone,
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o_RXPHALIGNDONE=rx_init.Xxphaligndone,
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i_RXUSERRDY=rx_init.Xxuserrdy,
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# RX AFE
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p_RX_DFE_XYD_CFG=0,
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i_RXDFEXYDEN=1,
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i_RXDFEXYDHOLD=0,
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i_RXDFEXYDOVRDEN=0,
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i_RXLPMEN=0,
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# RX clock
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p_RXBUF_EN="FALSE",
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p_RX_XCLK_SEL="RXUSR",
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i_RXDDIEN=1,
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i_RXSYSCLKSEL=0b00,
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i_RXOUTCLKSEL=0b010,
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o_RXOUTCLK=self.rxoutclk,
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i_RXUSRCLK=ClockSignal("rtio_rx0"),
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i_RXUSRCLK2=ClockSignal("rtio_rx0"),
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p_RXCDR_CFG=0x03000023FF10100020,
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# RX Clock Correction Attributes
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p_CLK_CORRECT_USE="FALSE",
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p_CLK_COR_SEQ_1_1=0b0100000000,
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p_CLK_COR_SEQ_2_1=0b0100000000,
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p_CLK_COR_SEQ_1_ENABLE=0b1111,
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p_CLK_COR_SEQ_2_ENABLE=0b1111,
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# RX data
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p_RX_DATA_WIDTH=20,
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p_RX_INT_DATAWIDTH=0,
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o_RXDISPERR=Cat(rxdata[9], rxdata[19]),
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o_RXCHARISK=Cat(rxdata[8], rxdata[18]),
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o_RXDATA=Cat(rxdata[:8], rxdata[10:18]),
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# Pads
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i_GTXRXP=rx_pads.p,
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i_GTXRXN=rx_pads.n,
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o_GTXTXP=tx_pads.p,
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o_GTXTXN=tx_pads.n,
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)
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tx_reset_deglitched = Signal()
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tx_reset_deglitched.attr.add("no_retiming")
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self.sync += tx_reset_deglitched.eq(~tx_init.done)
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self.specials += [
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Instance("BUFG", i_I=self.txoutclk, o_O=self.cd_rtio.clk),
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AsyncResetSynchronizer(self.cd_rtio, tx_reset_deglitched)
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]
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rx_reset_deglitched = Signal()
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rx_reset_deglitched.attr.add("no_retiming")
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self.sync.rtio += rx_reset_deglitched.eq(~rx_init.done)
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self.specials += [
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Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_rtio_rx0.clk),
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AsyncResetSynchronizer(self.cd_rtio_rx0, rx_reset_deglitched)
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]
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chan = self.channels[0]
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self.comb += [
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txdata.eq(Cat(chan.encoder.output[0], chan.encoder.output[1])),
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chan.decoders[0].input.eq(rxdata[:10]),
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chan.decoders[1].input.eq(rxdata[10:])
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]
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clock_aligner = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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BruteforceClockAligner(0b0101111100, self.rtio_clk_freq))
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self.submodules += clock_aligner
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self.comb += [
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clock_aligner.rxdata.eq(rxdata),
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rx_init.restart.eq(clock_aligner.restart),
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chan.rx_ready.eq(clock_aligner.ready)
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]
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class GTX_1000BASE_BX10(GTX_20X):
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rtio_clk_freq = 62.5e6
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class RXSynchronizer(Module, AutoCSR):
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"""Delays the data received in the rtio_rx domain by a configurable amount
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so that it meets s/h in the rtio domain, and recapture it in the rtio
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domain. This has fixed latency.
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Since Xilinx doesn't provide decent on-chip delay lines, we implement the
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delay with MMCM that provides a clock and a finely configurable phase, used
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to resample the data.
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The phase has to be determined either empirically or by making sense of the
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Xilinx scriptures (when existent) and should be constant for a given design
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placement.
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"""
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def __init__(self, rtio_clk_freq, initial_phase=0.0):
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self.phase_shift = CSR()
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self.phase_shift_done = CSRStatus()
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self.clock_domains.cd_rtio_delayed = ClockDomain()
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mmcm_output = Signal()
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mmcm_fb = Signal()
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mmcm_locked = Signal()
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# maximize VCO frequency to maximize phase shift resolution
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mmcm_mult = 1200e6//rtio_clk_freq
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self.specials += [
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Instance("MMCME2_ADV",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio_rx"),
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i_RST=ResetSignal("rtio_rx"),
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i_CLKINSEL=1, # yes, 1=CLKIN1 0=CLKIN2
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p_CLKFBOUT_MULT_F=mmcm_mult,
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p_CLKOUT0_DIVIDE_F=mmcm_mult,
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p_CLKOUT0_PHASE=initial_phase,
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p_DIVCLK_DIVIDE=1,
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# According to Xilinx, there is no guarantee of input/output
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# phase relationship when using internal feedback. We assume
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# here that the input/ouput skew is constant to save BUFGs.
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o_CLKFBOUT=mmcm_fb,
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i_CLKFBIN=mmcm_fb,
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p_CLKOUT0_USE_FINE_PS="TRUE",
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o_CLKOUT0=mmcm_output,
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o_LOCKED=mmcm_locked,
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i_PSCLK=ClockSignal(),
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i_PSEN=self.phase_shift.re,
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i_PSINCDEC=self.phase_shift.r,
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o_PSDONE=self.phase_shift_done.status,
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),
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Instance("BUFR", i_I=mmcm_output, o_O=self.cd_rtio_delayed.clk),
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AsyncResetSynchronizer(self.cd_rtio_delayed, ~mmcm_locked)
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]
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def resync(self, signal):
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delayed = Signal.like(signal, related=signal)
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synchronized = Signal.like(signal, related=signal)
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self.sync.rtio_delayed += delayed.eq(signal)
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self.sync.rtio += synchronized.eq(delayed)
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return synchronized
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@ -1,226 +0,0 @@
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from math import ceil
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from functools import reduce
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from operator import add
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from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.genlib.misc import WaitTimer
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from migen.genlib.fsm import FSM
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class GTXInit(Module):
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# Based on LiteSATA by Enjoy-Digital
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def __init__(self, sys_clk_freq, rx):
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self.done = Signal()
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self.restart = Signal()
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# GTX signals
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self.cplllock = Signal()
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self.gtXxreset = Signal()
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self.Xxresetdone = Signal()
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self.Xxdlysreset = Signal()
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self.Xxdlysresetdone = Signal()
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self.Xxphaligndone = Signal()
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self.Xxuserrdy = Signal()
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# # #
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# Double-latch transceiver asynch outputs
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cplllock = Signal()
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Xxresetdone = Signal()
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Xxdlysresetdone = Signal()
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Xxphaligndone = Signal()
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self.specials += [
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MultiReg(self.cplllock, cplllock),
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MultiReg(self.Xxresetdone, Xxresetdone),
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MultiReg(self.Xxdlysresetdone, Xxdlysresetdone),
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MultiReg(self.Xxphaligndone, Xxphaligndone),
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]
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# Deglitch FSM outputs driving transceiver asynch inputs
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gtXxreset = Signal()
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Xxdlysreset = Signal()
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Xxuserrdy = Signal()
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self.sync += [
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self.gtXxreset.eq(gtXxreset),
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self.Xxdlysreset.eq(Xxdlysreset),
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self.Xxuserrdy.eq(Xxuserrdy)
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]
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# After configuration, transceiver resets have to stay low for
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# at least 500ns (see AR43482)
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startup_cycles = ceil(500*sys_clk_freq/1000000000)
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startup_timer = WaitTimer(startup_cycles)
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self.submodules += startup_timer
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startup_fsm = FSM(reset_state="INITIAL")
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self.submodules += startup_fsm
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if rx:
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cdr_stable_timer = WaitTimer(1024)
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self.submodules += cdr_stable_timer
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Xxphaligndone_r = Signal(reset=1)
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Xxphaligndone_rising = Signal()
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self.sync += Xxphaligndone_r.eq(Xxphaligndone)
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self.comb += Xxphaligndone_rising.eq(Xxphaligndone & ~Xxphaligndone_r)
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startup_fsm.act("INITIAL",
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startup_timer.wait.eq(1),
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If(startup_timer.done, NextState("RESET_GTX"))
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)
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startup_fsm.act("RESET_GTX",
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gtXxreset.eq(1),
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NextState("WAIT_CPLL")
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)
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startup_fsm.act("WAIT_CPLL",
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gtXxreset.eq(1),
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If(cplllock, NextState("RELEASE_RESET"))
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)
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# Release GTX reset and wait for GTX resetdone
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# (from UG476, GTX is reset on falling edge
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# of gttxreset)
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if rx:
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startup_fsm.act("RELEASE_RESET",
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Xxuserrdy.eq(1),
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cdr_stable_timer.wait.eq(1),
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If(Xxresetdone & cdr_stable_timer.done, NextState("ALIGN"))
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)
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else:
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startup_fsm.act("RELEASE_RESET",
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Xxuserrdy.eq(1),
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If(Xxresetdone, NextState("ALIGN"))
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)
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# Start delay alignment (pulse)
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startup_fsm.act("ALIGN",
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Xxuserrdy.eq(1),
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Xxdlysreset.eq(1),
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NextState("WAIT_ALIGN")
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)
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# Wait for delay alignment
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startup_fsm.act("WAIT_ALIGN",
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Xxuserrdy.eq(1),
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If(Xxdlysresetdone, NextState("WAIT_FIRST_ALIGN_DONE"))
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)
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# Wait 2 rising edges of rxphaligndone
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# (from UG476 in buffer bypass config)
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startup_fsm.act("WAIT_FIRST_ALIGN_DONE",
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Xxuserrdy.eq(1),
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If(Xxphaligndone_rising, NextState("WAIT_SECOND_ALIGN_DONE"))
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)
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startup_fsm.act("WAIT_SECOND_ALIGN_DONE",
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Xxuserrdy.eq(1),
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If(Xxphaligndone_rising, NextState("READY"))
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)
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startup_fsm.act("READY",
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Xxuserrdy.eq(1),
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self.done.eq(1),
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If(self.restart, NextState("RESET_GTX"))
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)
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# Changes the phase of the transceiver RX clock to align the comma to
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# the LSBs of RXDATA, fixing the latency.
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#
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# This is implemented by repeatedly resetting the transceiver until it
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# gives out the correct phase. Each reset gives a random phase.
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#
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# If Xilinx had designed the GTX transceiver correctly, RXSLIDE_MODE=PMA
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# would achieve this faster and in a cleaner way. But:
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# * the phase jumps are of 2 UI at every second RXSLIDE pulse, instead
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# of 1 UI at every pulse. It is unclear what the latency becomes.
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# * RXSLIDE_MODE=PMA cannot be used with the RX buffer bypassed.
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# Those design flaws make RXSLIDE_MODE=PMA yet another broken and useless
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# transceiver "feature".
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#
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# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
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# compared to the usual 8b10b binary representation.
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class BruteforceClockAligner(Module):
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def __init__(self, comma, rtio_clk_freq, check_period=6e-3):
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self.rxdata = Signal(20)
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self.restart = Signal()
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self.ready = Signal()
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check_max_val = ceil(check_period*rtio_clk_freq)
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check_counter = Signal(max=check_max_val+1)
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check = Signal()
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reset_check_counter = Signal()
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self.sync.rtio += [
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check.eq(0),
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If(reset_check_counter,
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check_counter.eq(check_max_val)
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).Else(
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If(check_counter == 0,
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check.eq(1),
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check_counter.eq(check_max_val)
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).Else(
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check_counter.eq(check_counter-1)
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)
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)
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]
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checks_reset = PulseSynchronizer("rtio", "rtio_rx")
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self.submodules += checks_reset
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comma_n = ~comma & 0b1111111111
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comma_seen_rxclk = Signal()
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comma_seen = Signal()
|
||||
comma_seen_rxclk.attr.add("no_retiming")
|
||||
self.specials += MultiReg(comma_seen_rxclk, comma_seen)
|
||||
self.sync.rtio_rx += \
|
||||
If(checks_reset.o,
|
||||
comma_seen_rxclk.eq(0)
|
||||
).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n),
|
||||
comma_seen_rxclk.eq(1)
|
||||
)
|
||||
|
||||
error_seen_rxclk = Signal()
|
||||
error_seen = Signal()
|
||||
error_seen_rxclk.attr.add("no_retiming")
|
||||
self.specials += MultiReg(error_seen_rxclk, error_seen)
|
||||
rx1cnt = Signal(max=11)
|
||||
self.sync.rtio_rx += [
|
||||
rx1cnt.eq(reduce(add, [self.rxdata[i] for i in range(10)])),
|
||||
If(checks_reset.o,
|
||||
error_seen_rxclk.eq(0)
|
||||
).Elif((rx1cnt != 4) & (rx1cnt != 5) & (rx1cnt != 6),
|
||||
error_seen_rxclk.eq(1)
|
||||
)
|
||||
]
|
||||
|
||||
fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="WAIT_COMMA"))
|
||||
self.submodules += fsm
|
||||
|
||||
fsm.act("WAIT_COMMA",
|
||||
If(check,
|
||||
# Errors are still OK at this stage, as the transceiver
|
||||
# has just been reset and may output garbage data.
|
||||
If(comma_seen,
|
||||
NextState("WAIT_NOERROR")
|
||||
).Else(
|
||||
self.restart.eq(1)
|
||||
),
|
||||
checks_reset.i.eq(1)
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_NOERROR",
|
||||
If(check,
|
||||
If(comma_seen & ~error_seen,
|
||||
NextState("READY")
|
||||
).Else(
|
||||
self.restart.eq(1),
|
||||
NextState("WAIT_COMMA")
|
||||
),
|
||||
checks_reset.i.eq(1)
|
||||
)
|
||||
)
|
||||
fsm.act("READY",
|
||||
reset_check_counter.eq(1),
|
||||
self.ready.eq(1),
|
||||
If(error_seen,
|
||||
checks_reset.i.eq(1),
|
||||
self.restart.eq(1),
|
||||
NextState("WAIT_COMMA")
|
||||
)
|
||||
)
|
||||
|
|
@ -1,116 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import argparse
|
||||
|
||||
from migen import *
|
||||
from migen.build.generic_platform import *
|
||||
|
||||
from misoc.cores import spi as spi_csr
|
||||
from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
|
||||
from misoc.integration.builder import builder_args, builder_argdict
|
||||
|
||||
from artiq.gateware.amp import AMPSoC, build_artiq_soc
|
||||
from artiq.gateware import rtio
|
||||
from artiq.gateware.rtio.phy import ttl_simple
|
||||
from artiq.gateware.drtio.transceiver import gtx_7series
|
||||
from artiq.gateware.drtio import DRTIOMaster
|
||||
from artiq import __version__ as artiq_version
|
||||
|
||||
|
||||
class Master(MiniSoC, AMPSoC):
|
||||
mem_map = {
|
||||
"cri_con": 0x10000000,
|
||||
"rtio": 0x20000000,
|
||||
"rtio_dma": 0x30000000,
|
||||
"drtio_aux": 0x50000000,
|
||||
"mailbox": 0x70000000
|
||||
}
|
||||
mem_map.update(MiniSoC.mem_map)
|
||||
|
||||
def __init__(self, **kwargs):
|
||||
MiniSoC.__init__(self,
|
||||
cpu_type="or1k",
|
||||
sdram_controller_type="minicon",
|
||||
l2_size=128*1024,
|
||||
ident=artiq_version,
|
||||
ethmac_nrxslots=4,
|
||||
ethmac_ntxslots=4,
|
||||
**kwargs)
|
||||
AMPSoC.__init__(self)
|
||||
|
||||
platform = self.platform
|
||||
|
||||
self.comb += platform.request("sfp_tx_disable_n").eq(1)
|
||||
tx_pads = platform.request("sfp_tx")
|
||||
rx_pads = platform.request("sfp_rx")
|
||||
|
||||
# 1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
|
||||
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
|
||||
clock_pads=platform.request("sgmii_clock"),
|
||||
tx_pads=tx_pads,
|
||||
rx_pads=rx_pads,
|
||||
sys_clk_freq=self.clk_freq,
|
||||
clock_div2=True)
|
||||
|
||||
self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
|
||||
DRTIOMaster(self.transceiver.channels[0]))
|
||||
self.csr_devices.append("drtio0")
|
||||
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
|
||||
self.drtio0.aux_controller.bus)
|
||||
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
|
||||
self.config["HAS_DRTIO"] = None
|
||||
self.add_csr_group("drtio", ["drtio0"])
|
||||
self.add_memory_group("drtio_aux", ["drtio0_aux"])
|
||||
|
||||
self.comb += [
|
||||
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
|
||||
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
|
||||
]
|
||||
|
||||
rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
|
||||
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
|
||||
platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
self.transceiver.txoutclk, self.transceiver.rxoutclk)
|
||||
|
||||
rtio_channels = []
|
||||
for i in range(8):
|
||||
phy = ttl_simple.Output(platform.request("user_led", i))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
for sma in "user_sma_gpio_p", "user_sma_gpio_n":
|
||||
phy = ttl_simple.InOut(platform.request(sma))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
|
||||
self.csr_devices.append("rtio_core")
|
||||
|
||||
self.submodules.rtio = rtio.KernelInitiator()
|
||||
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
|
||||
rtio.DMA(self.get_native_sdram_if()))
|
||||
self.register_kernel_cpu_csrdevice("rtio")
|
||||
self.register_kernel_cpu_csrdevice("rtio_dma")
|
||||
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
||||
[self.rtio.cri, self.rtio_dma.cri],
|
||||
[self.rtio_core.cri, self.drtio0.cri])
|
||||
self.register_kernel_cpu_csrdevice("cri_con")
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="ARTIQ device binary builder / KC705 DRTIO master")
|
||||
builder_args(parser)
|
||||
soc_kc705_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = Master(**soc_kc705_argdict(args))
|
||||
build_artiq_soc(soc, builder_argdict(args))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -1,114 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import argparse
|
||||
import os
|
||||
|
||||
from migen import *
|
||||
from migen.build.generic_platform import *
|
||||
from misoc.cores import spi as spi_csr
|
||||
from misoc.cores import gpio
|
||||
from misoc.integration.builder import *
|
||||
from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
|
||||
|
||||
from artiq.gateware import rtio
|
||||
from artiq.gateware.rtio.phy import ttl_simple
|
||||
from artiq.gateware.drtio.transceiver import gtx_7series
|
||||
from artiq.gateware.drtio import DRTIOSatellite
|
||||
from artiq import __version__ as artiq_version
|
||||
from artiq import __artiq_dir__ as artiq_dir
|
||||
|
||||
|
||||
class Satellite(BaseSoC):
|
||||
mem_map = {
|
||||
"drtio_aux": 0x50000000,
|
||||
}
|
||||
mem_map.update(BaseSoC.mem_map)
|
||||
|
||||
def __init__(self, **kwargs):
|
||||
BaseSoC.__init__(self,
|
||||
cpu_type="or1k",
|
||||
sdram_controller_type="minicon",
|
||||
l2_size=128*1024,
|
||||
ident=artiq_version,
|
||||
**kwargs)
|
||||
|
||||
platform = self.platform
|
||||
|
||||
rtio_channels = []
|
||||
for i in range(8):
|
||||
phy = ttl_simple.Output(platform.request("user_led", i))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
for sma in "user_sma_gpio_p", "user_sma_gpio_n":
|
||||
phy = ttl_simple.InOut(platform.request(sma))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.comb += platform.request("sfp_tx_disable_n").eq(1)
|
||||
|
||||
# 1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
|
||||
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
|
||||
clock_pads=platform.request("si5324_clkout"),
|
||||
tx_pads=platform.request("sfp_tx"),
|
||||
rx_pads=platform.request("sfp_rx"),
|
||||
sys_clk_freq=self.clk_freq)
|
||||
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
|
||||
self.submodules.rx_synchronizer0 = rx0(gtx_7series.RXSynchronizer(
|
||||
self.transceiver.rtio_clk_freq, initial_phase=180.0))
|
||||
self.submodules.drtio0 = rx0(DRTIOSatellite(
|
||||
self.transceiver.channels[0], rtio_channels, self.rx_synchronizer0))
|
||||
self.csr_devices.append("rx_synchronizer0")
|
||||
self.csr_devices.append("drtio0")
|
||||
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
|
||||
self.drtio0.aux_controller.bus)
|
||||
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
|
||||
self.config["HAS_DRTIO"] = None
|
||||
self.add_csr_group("drtio", ["drtio0"])
|
||||
self.add_memory_group("drtio_aux", ["drtio0_aux"])
|
||||
|
||||
self.config["RTIO_FREQUENCY"] = str(self.transceiver.rtio_clk_freq/1e6)
|
||||
si5324_clkin = platform.request("si5324_clkin")
|
||||
self.specials += \
|
||||
Instance("OBUFDS",
|
||||
i_I=ClockSignal("rtio_rx0"),
|
||||
o_O=si5324_clkin.p, o_OB=si5324_clkin.n
|
||||
)
|
||||
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
|
||||
self.csr_devices.append("si5324_rst_n")
|
||||
i2c = self.platform.request("i2c")
|
||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
self.csr_devices.append("i2c")
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
self.config["HAS_SI5324"] = None
|
||||
|
||||
self.comb += [
|
||||
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
|
||||
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
|
||||
]
|
||||
|
||||
rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
|
||||
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
|
||||
platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
platform.lookup_request("clk200"),
|
||||
self.transceiver.txoutclk, self.transceiver.rxoutclk)
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="ARTIQ device binary builder / KC705 DRTIO satellite")
|
||||
builder_args(parser)
|
||||
soc_kc705_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = Satellite(**soc_kc705_argdict(args))
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.add_software_package("satman", os.path.join(artiq_dir, "firmware", "satman"))
|
||||
builder.build()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue