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sayma_amc: set bitstream and config parameters 

* slow down CCLK rate as there is additional loading
  on the signals
* single bit SPI for now until we know that quad SPI
  works
* set up

https://github.com/m-labs/artiq/issues/847
This commit is contained in:
Robert Jördens 2017-12-13 21:21:52 +08:00
parent 2917208d89
commit a9d0f253a5
1 changed files with 8 additions and 2 deletions
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10
artiq/gateware/targets/sayma_amc_standalone.py
View File

@ -120,8 +120,14 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
platform.toolchain.bitstream_commands.append(
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]")
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 3 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])
self.submodules.leds = gpio.GPIOOut(Cat(
platform.request("user_led", 0),