M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-29 05:03:34 +08:00
Code Issues Projects Releases Wiki Activity

sayma_rtm: derive clocks automatically

Browse Source 
* also don't add false paths unless necessary
This commit is contained in:
Robert Jördens 2018-01-23 11:00:55 +00:00
parent 7d1b3f37c9
commit 85102e191e
1 changed files with 0 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/gateware/targets/sayma_rtm.py
View File

@ -81,13 +81,7 @@ class SaymaRTM(Module):
csr_devices = []
self.submodules.crg = CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
clk_freq = 125e6
platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
platform.add_period_constraint(self.crg.cd_clk200.clk, 5.0)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_clk200.clk)
self.submodules.rtm_identifier = RTMIdentifier()
csr_devices.append("rtm_identifier")