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rtio: allow specifying glbl_fine_ts_width externally

pull/889/head
Sebastien Bourdeauducq 2017-09-23 22:34:55 +08:00
parent 5cf0693758
commit aa8fc81a87
2 changed files with 8 additions and 3 deletions
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9
artiq/gateware/rtio/core.py
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@ -14,7 +14,8 @@ from artiq.gateware.rtio.input_collector import *
class Core(Module, AutoCSR):
def __init__(self, channels, lane_count=8, fifo_depth=128):
def __init__(self, channels, lane_count=8, fifo_depth=128,
glbl_fine_ts_width=None):
self.cri = cri.Interface()
self.reset = CSR()
self.reset_phy = CSR()
@ -53,10 +54,14 @@ class Core(Module, AutoCSR):
self.specials += AsyncResetSynchronizer(self.cd_rio_phy, cmd_reset_phy)
# TSC
glbl_fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
chan_fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
for channel in channels),
max(rtlink.get_fine_ts_width(channel.interface.i)
for channel in channels))
if glbl_fine_ts_width is None:
glbl_fine_ts_width = chan_fine_ts_width
assert glbl_fine_ts_width >= chan_fine_ts_width
coarse_ts = Signal(64-glbl_fine_ts_width)
self.sync.rtio += coarse_ts.eq(coarse_ts + 1)
coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts))

2
artiq/gateware/targets/kc705_drtio_master.py
View File

@ -94,7 +94,7 @@ class Master(MiniSoC, AMPSoC):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
self.submodules.rtio_core = rtio.Core(rtio_channels, glbl_fine_ts_width=3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()