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ad5360: port to spi2
* kc705 nist_clock target gateware * coredevice driver * moninj code * test/example/device_db This is untested as we don't have a AD5360 board right now. Will be tested with Zotino v1.1 m-labs/artiq#926
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@ -6,14 +6,16 @@ time is an error.
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"""
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from artiq.language.core import (kernel, portable, delay_mu, delay)
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from artiq.language.core import (kernel, portable, delay_mu, delay, now_mu,
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at_mu)
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from artiq.language.units import ns, us
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from artiq.coredevice import spi
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from artiq.coredevice import spi2 as spi
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# Designed from the data sheets and somewhat after the linux kernel
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# iio driver.
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_AD5360_SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_CS_POLARITY |
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_AD5360_SPI_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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@ -27,6 +29,7 @@ _AD5360_CMD_SPECIAL = 0 << 22
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def _AD5360_WRITE_CHANNEL(c):
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return (c + 8) << 16
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_AD5360_SPECIAL_NOP = 0 << 16
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_AD5360_SPECIAL_CONTROL = 1 << 16
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_AD5360_SPECIAL_OFS0 = 2 << 16
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@ -38,6 +41,7 @@ _AD5360_SPECIAL_READ = 5 << 16
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def _AD5360_READ_CHANNEL(ch):
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return (ch + 8) << 7
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_AD5360_READ_X1A = 0x000 << 7
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_AD5360_READ_X1B = 0x040 << 7
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_AD5360_READ_OFFSET = 0x080 << 7
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@ -57,31 +61,34 @@ class AD5360:
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(optional). Needs to be explicitly initialized to high.
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:param chip_select: Value to drive on the chip select lines
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during transactions.
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:param div_write: SPI clock divider during writes
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:param div_read: SPI clock divider during reads
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"""
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kernel_invariants = {"bus", "core", "chip_select", "div_read", "div_write"}
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def __init__(self, dmgr, spi_device, ldac_device=None, chip_select=1):
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def __init__(self, dmgr, spi_device, ldac_device=None, chip_select=1,
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div_write=4, div_read=7):
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self.core = dmgr.get("core")
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self.bus = dmgr.get(spi_device)
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if ldac_device is not None:
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self.ldac = dmgr.get(ldac_device)
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self.chip_select = chip_select
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# write: 2*8ns >= 10ns = t_6 (clk falling to cs_n rising)
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# 4*8ns >= 20ns = t_1 (clk cycle time)
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self.div_write = div_write
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# read: 4*8*ns >= 25ns = t_22 (clk falling to miso valid)
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self.div_read = div_read
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@kernel
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def setup_bus(self, write_div=4, read_div=7):
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def setup_bus(self):
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"""Configure the SPI bus and the SPI transaction parameters
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for this device. This method has to be called before any other method
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if the bus has been used to access a different device in the meantime.
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This method advances the timeline by the duration of two
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RTIO-to-Wishbone bus transactions.
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:param write_div: Write clock divider.
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:param read_div: Read clock divider.
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This method advances the timeline by one coarse RTIO cycle.
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"""
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# write: 2*8ns >= 10ns = t_6 (clk falling to cs_n rising)
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# read: 4*8*ns >= 25ns = t_22 (clk falling to miso valid)
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self.bus.set_config_mu(_AD5360_SPI_CONFIG, write_div, read_div)
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self.bus.set_xfer(self.chip_select, 24, 0)
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self.bus.set_config_mu(_AD5360_SPI_CONFIG, 24, self.div_write,
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self.chip_select)
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@kernel
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def write(self, data):
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@ -126,8 +133,8 @@ class AD5360:
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def read_channel_sync(self, channel=0, op=_AD5360_READ_X1A):
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"""Read a channel register.
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This method advances the timeline by the duration of :meth:`write` plus
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three RTIO-to-Wishbone transactions.
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This method advances the timeline by the duration of two :meth:`write`
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plus two coarse RTIO cycles.
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:param channel: Channel number to read from.
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:param op: Operation to perform, one of :const:`_AD5360_READ_X1A`,
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@ -138,11 +145,13 @@ class AD5360:
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channel &= 0x3f
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_READ | op |
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_AD5360_READ_CHANNEL(channel))
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self.bus.set_xfer(self.chip_select, 0, 24)
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self.bus.set_config_mu(_AD5360_SPI_CONFIG | spi.SPI_INPUT, 24,
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self.div_read, self.chip_select)
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delay(270*ns) # t_21 min sync high in readback
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_NOP)
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self.bus.read_async()
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self.bus.set_xfer(self.chip_select, 24, 0)
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return self.bus.input_async() & 0xffff
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self.bus.set_config_mu(_AD5360_SPI_CONFIG, 24,
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self.div_write, self.chip_select)
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return self.bus.read() & 0xffff
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@kernel
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def load(self):
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@ -168,15 +177,13 @@ class AD5360:
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:const:`_AD5360_CMD_OFFSET`, :const:`_AD5360_CMD_GAIN`
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(default: :const:`_AD5360_CMD_DATA`).
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"""
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t0 = now_mu()
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# t10 max busy low for one channel
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t_10 = self.core.seconds_to_mu(1.5*us)
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# compensate all delays that will be applied
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delay_mu(-len(values)*(self.bus.xfer_period_mu +
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self.bus.write_period_mu +
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self.bus.ref_period_mu) -
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3*self.bus.ref_period_mu -
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self.core.seconds_to_mu(1.5*us))
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delay_mu(-len(values)*self.bus.xfer_period_mu-t_10)
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for i in range(len(values)):
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self.write_channel(i, values[i], op)
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delay_mu(3*self.bus.ref_period_mu + # latency alignment ttl to spi
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self.core.seconds_to_mu(1.5*us)) # t10 max busy low for one channel
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delay_mu(t_10)
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self.load()
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delay_mu(-2*self.bus.ref_period_mu) # load(), t13
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at_mu(t0)
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@ -173,7 +173,7 @@ device_db = {
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},
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"spi_zotino": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 30}
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},
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@ -187,7 +187,12 @@ device_db = {
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"type": "local",
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"module": "artiq.coredevice.ad5360",
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"class": "AD5360",
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"arguments": {"spi_device": "spi_zotino", "ldac_device": "ttl_zotino_ldac"}
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"arguments": {
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"spi_device": "spi_zotino",
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"ldac_device": "ttl_zotino_ldac",
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"div_write": 30,
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"div_read": 40
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}
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},
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"spi_urukul": {
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@ -13,7 +13,7 @@ class AD5360Test(EnvExperiment):
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self.core.reset()
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delay(5*ms) # build slack for shift register set
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self.fmcdio_dirctl.set(self, 0x00008800)
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self.dac.setup_bus(write_div=30, read_div=40)
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self.dac.setup_bus()
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self.dac.write_offsets()
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self.led.on()
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delay(400*us)
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@ -1,6 +1,6 @@
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from migen import *
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from artiq.coredevice.spi import SPI_XFER_ADDR, SPI_DATA_ADDR
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from artiq.coredevice.spi2 import SPI_CONFIG_ADDR, SPI_DATA_ADDR
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from artiq.coredevice.ad5360 import _AD5360_CMD_DATA, _AD5360_WRITE_CHANNEL
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@ -22,20 +22,20 @@ class AD5360Monitor(Module):
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If(ldac_oif.stb & ttl_level_adr & ~ldac_oif.data[0],
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[probe.eq(write_target) for probe, write_target in zip(self.probes, write_targets)]
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)
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spi_oif = spi_rtlink.o
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selected = Signal()
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if cs_onehot:
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self.sync.rio_phy += [
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If(spi_oif.stb & (spi_oif.address == SPI_XFER_ADDR),
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selected.eq(spi_oif.data[cs_no])
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If(spi_oif.stb & (spi_oif.address == SPI_CONFIG_ADDR),
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selected.eq(spi_oif.data[24 + cs_no])
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)
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]
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else:
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self.sync.rio_phy += [
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If(spi_oif.stb & (spi_oif.address == SPI_XFER_ADDR),
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selected.eq(spi_oif.data[:16] == cs_no)
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If(spi_oif.stb & (spi_oif.address == SPI_CONFIG_ADDR),
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selected.eq(spi_oif.data[24:] == cs_no)
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)
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]
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sdac_phy = spi.SPIMaster(self.platform.request("zotino_spi_p"),
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self.platform.request("zotino_spi_n"))
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sdac_phy = spi2.SPIMaster(self.platform.request("zotino_spi_p"),
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self.platform.request("zotino_spi_n"))
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self.submodules += sdac_phy
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rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4))
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