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drtio: implement Si5324 phaser gateware and partial firmware support
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@ -1,6 +1,6 @@
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use core::result;
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use board::clock;
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#[cfg(not(si5324_soft_reset))]
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#[cfg(any(not(si5324_soft_reset), has_si_phaser))]
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use board::csr;
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use i2c;
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@ -47,6 +47,11 @@ pub struct FrequencySettings {
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pub crystal_ref: bool
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}
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pub enum Input {
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Ckin1,
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Ckin2,
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}
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fn map_frequency_settings(settings: &FrequencySettings) -> Result<FrequencySettings> {
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if settings.nc1_ls != 0 && (settings.nc1_ls % 2) == 1 {
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return Err("NC1_LS must be 0 or even")
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@ -160,8 +165,11 @@ fn has_xtal() -> Result<bool> {
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Ok((read(129)? & 0x01) == 0) // LOSX_INT=0
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}
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fn has_clkin2() -> Result<bool> {
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Ok((read(129)? & 0x04) == 0) // LOS2_INT=0
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fn has_ckin(input: Input) -> Result<bool> {
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match input {
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Input::Ckin1 => Ok((read(129)? & 0x02) == 0), // LOS1_INT=0
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Input::Ckin2 => Ok((read(129)? & 0x04) == 0), // LOS2_INT=0
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}
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}
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fn locked() -> Result<bool> {
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@ -180,7 +188,7 @@ fn monitor_lock() -> Result<()> {
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Ok(())
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}
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pub fn setup(settings: &FrequencySettings) -> Result<()> {
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pub fn setup(settings: &FrequencySettings, input: Input) -> Result<()> {
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let s = map_frequency_settings(settings)?;
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#[cfg(not(si5324_soft_reset))]
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@ -203,12 +211,16 @@ pub fn setup(settings: &FrequencySettings) -> Result<()> {
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#[cfg(si5324_soft_reset)]
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soft_reset()?;
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let cksel_reg = match input {
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Input::Ckin1 => 0b00,
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Input::Ckin2 => 0b01,
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};
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if settings.crystal_ref {
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write(0, read(0)? | 0x40)?; // FREE_RUN=1
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}
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write(2, (read(2)? & 0x0f) | (s.bwsel << 4))?;
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write(21, read(21)? & 0xfe)?; // CKSEL_PIN=0
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write(3, (read(3)? & 0x3f) | (0b01 << 6) | 0x10)?; // CKSEL_REG=b01 SQ_ICAL=1
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write(3, (read(3)? & 0x3f) | (cksel_reg << 6) | 0x10)?; // CKSEL_REG, SQ_ICAL=1
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write(4, (read(4)? & 0x3f) | (0b00 << 6))?; // AUTOSEL_REG=b00
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write(6, (read(6)? & 0xc0) | 0b111111)?; // SFOUT2_REG=b111 SFOUT1_REG=b111
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write(25, (s.n1_hs << 5 ) as u8)?;
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@ -233,20 +245,40 @@ pub fn setup(settings: &FrequencySettings) -> Result<()> {
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if !has_xtal()? {
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return Err("Si5324 misses XA/XB signal");
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}
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if !has_clkin2()? {
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return Err("Si5324 misses CLKIN2 signal");
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if !has_ckin(input)? {
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return Err("Si5324 misses clock input signal");
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}
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monitor_lock()?;
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Ok(())
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}
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pub fn select_ext_input(external: bool) -> Result<()> {
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if external {
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write(3, (read(3)? & 0x3f) | (0b00 << 6))?; // CKSEL_REG=b00
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} else {
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write(3, (read(3)? & 0x3f) | (0b01 << 6))?; // CKSEL_REG=b01
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pub fn select_input(input: Input) -> Result<()> {
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let cksel_reg = match input {
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Input::Ckin1 => 0b00,
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Input::Ckin2 => 0b01,
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};
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write(3, (read(3)? & 0x3f) | (cksel_reg << 6))?;
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if !has_ckin(input)? {
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return Err("Si5324 misses clock input signal");
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}
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monitor_lock()?;
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Ok(())
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}
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#[cfg(has_si_phaser)]
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pub fn select_recovered_clock(rc: bool) -> Result<()> {
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write(3, (read(3)? & 0xdf) | (1 << 5))?; // DHOLD=1
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unsafe {
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csr::si_phaser::switch_clocks_write(if rc { 1 } else { 0 });
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}
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write(3, (read(3)? & 0xdf) | (1 << 5))?; // DHOLD=0
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monitor_lock()?;
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Ok(())
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}
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#[cfg(has_si_phaser)]
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pub fn calibrate_skew() -> Result<()> {
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// TODO: implement
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Ok(())
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}
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@ -152,7 +152,7 @@ fn setup_si5324_as_synthesizer()
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bwsel : 3,
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crystal_ref: true
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};
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board_artiq::si5324::setup(&SI5324_SETTINGS).expect("cannot initialize Si5324");
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board_artiq::si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin2).expect("cannot initialize Si5324");
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}
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#[cfg(has_ethmac)]
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@ -195,14 +195,14 @@ fn process_errors() {
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#[cfg(rtio_frequency = "150.0")]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 4,
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= si5324::FrequencySettings {
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n1_hs : 6,
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nc1_ls : 6,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 9370,
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n32 : 7139,
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bwsel : 3,
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n2_ls : 270,
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n31 : 75,
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n32 : 75,
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bwsel : 4,
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crystal_ref: true
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};
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@ -225,7 +225,7 @@ fn startup() {
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/* must be the first SPI init because of HMC830 SPI mode selection */
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hmc830_7043::init().expect("cannot initialize HMC830/7043");
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i2c::init();
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si5324::setup(&SI5324_SETTINGS).expect("cannot initialize Si5324");
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si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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@ -235,7 +235,8 @@ fn startup() {
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process_errors();
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}
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info!("link is up, switching to recovered clock");
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si5324::select_ext_input(true).expect("failed to switch clocks");
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si5324::select_recovered_clock(true).expect("failed to switch clocks");
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si5324::calibrate_skew().expect("failed to calibrate skew");
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drtio_reset(false);
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drtio_reset_phy(false);
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while drtio_link_rx_up() {
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@ -245,7 +246,7 @@ fn startup() {
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drtio_reset_phy(true);
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drtio_reset(true);
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info!("link is down, switching to local crystal clock");
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si5324::select_ext_input(false).expect("failed to switch clocks");
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si5324::select_recovered_clock(false).expect("failed to switch clocks");
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}
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}
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85
artiq/gateware/drtio/si_phaser.py
Normal file
85
artiq/gateware/drtio/si_phaser.py
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@ -0,0 +1,85 @@
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from migen import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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# This code assumes 125MHz system clock and 150MHz RTIO frequency.
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class SiPhaser7Series(Module, AutoCSR):
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def __init__(self, si5324_clkin, si5324_clkout_fabric):
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self.switch_clocks = CSRStorage()
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self.phase_shift = CSR()
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self.phase_shift_done = CSRStatus()
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self.sample_result = CSRStatus()
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# 125MHz system clock to 150MHz. VCO @ 625MHz.
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# Used to provide a startup clock to the transceiver through the Si,
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# we do not use the crystal reference so that the PFD (f3) frequency
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# can be high.
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mmcm_freerun_fb = Signal()
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mmcm_freerun_output = Signal()
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self.specials += \
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/125e6,
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i_CLKIN1=ClockSignal("sys"),
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i_RST=ResetSignal("sys"),
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p_CLKFBOUT_MULT_F=6.0, p_DIVCLK_DIVIDE=1,
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o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb,
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p_CLKOUT0_DIVIDE_F=5.0, o_CLKOUT0=mmcm_freerun_output,
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)
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# 150MHz to 150MHz with controllable phase shift, VCO @ 1200MHz.
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# Inserted between CDR and output to Si, used to correct
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# non-determinstic skew of Si5324.
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mmcm_ps_fb = Signal()
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mmcm_ps_output = Signal()
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self.specials += \
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Instance("MMCME2_ADV",
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p_CLKIN1_PERIOD=1e9/150e6,
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i_CLKIN1=ClockSignal("rtio_rx0"),
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i_RST=ResetSignal("rtio_rx0"),
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i_CLKINSEL=1, # yes, 1=CLKIN1 0=CLKIN2
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p_CLKFBOUT_MULT_F=8.0,
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p_CLKOUT0_DIVIDE_F=8.0,
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p_DIVCLK_DIVIDE=1,
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o_CLKFBOUT=mmcm_ps_fb, i_CLKFBIN=mmcm_ps_fb,
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p_CLKOUT0_USE_FINE_PS="TRUE",
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o_CLKOUT0=mmcm_ps_output,
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i_PSCLK=ClockSignal(),
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i_PSEN=self.phase_shift.re,
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i_PSINCDEC=self.phase_shift.r,
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o_PSDONE=self.phase_shift_done.status,
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)
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si5324_clkin_se = Signal()
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self.specials += [
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Instance("BUFGMUX",
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i_I0=mmcm_freerun_output,
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i_I1=mmcm_ps_output,
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i_S=self.switch_clocks.storage,
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o_O=si5324_clkin_se
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),
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Instance("OBUFDS",
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i_I=si5324_clkin_se,
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o_O=si5324_clkin.p, o_OB=si5324_clkin.n
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)
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]
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si5324_clkout_se = Signal()
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self.specials += \
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Instance("IBUFDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="TRUE",
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i_I=si5324_clkout_fabric.p, i_IB=si5324_clkout_fabric.n,
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o_O=si5324_clkout_se),
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clkout_sample1 = Signal() # IOB register
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self.sync.rtio_rx0 += clkout_sample1.eq(si5324_clkout_se)
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self.specials += MultiReg(clkout_sample1, self.sample_result.status)
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@ -21,6 +21,7 @@ from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.si_phaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
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from artiq.build_soc import build_artiq_soc
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@ -573,12 +574,11 @@ class Satellite(BaseSoC):
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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si5324_clkin = platform.request("si5324_clkin")
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self.specials += \
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Instance("OBUFDS",
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i_I=ClockSignal("rtio_rx0"),
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o_O=si5324_clkin.p, o_OB=si5324_clkin.n
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)
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self.submodules.si_phaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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si5324_clkout_fabric=platform.request("si5324_clkout_fabric")
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)
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self.csr_devices.append("si_phaser")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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